CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 40

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

Asynchronous Byte-Packed
Asynchronous byte-packed mode contains the same features as
asynchronous decoded, but with support for 10-bit source data
(BYTE8/10* is LOW). The received characters are decoded first
back into 8-bit data characters, which are then reassembled into
10-bit source data.
Because of the time difference involved with the packing and
unpacking operations, this mode can only be used with the
internal FIFOs enabled.
When receiving extended commands, the larger 10-bit character
size enlarges the extended command space to 1024 (2
possible commands codes.
When receiving a serial address, the larger 10-bit character size
also increases the Serial Address Register to 10 bits. This allows
up to 10 separate domains for multicast addressing or 1024
unique addresses for unicast addressing.
Asynchronous Undecoded
In Asynchronous Undecoded modes, the Receive FIFO is
enabled (FIFOBYP* is HIGH and ENCBYP* is LOW). This
means that all characters received from the serial interface are
written to the Receive FIFO before being passed to the output
register. The Deserializer operates synchronous to the
recovered bit-clock, which is divided by 10 or 12 to generate the
Receive FIFO write clock. Data is read from the Receive FIFO,
using the RXCLK input clock, when addressed by AM* and
selected by RXEN*.
These modes are usually used for products containing external
decoders or descramblers, that must meet specific protocol
requirements. New data may be read from the Receive FIFO any
time that the FIFO status flags indicate a non-empty condition
(RXEMPTY* is deasserted). To ensure that data is not lost
through a FIFO overflow, the Receive FIFO must be read faster
than data is loaded into the Receive FIFO.
If the receiver is to provide framed characters, it is necessary for
the transmit end to include C5.0 (K28.5) characters in the data
stream. This can be done by:
■
■
■
■
Document #: 38-02008 Rev. *G
Operating the transmitter in encoded mode and writing C5.0
characters into the data stream
Operating the transmitter in pre-encoded mode and writing the
10-bit value for an encoded C5.0 character to the data stream
(1100000101 or 0011111010)
Deasserting TXEN* when the transmitter is operated in
synchronous mode
Asserting TXHALT*, or by allowing the transmit FIFO to go
empty when it is operated in asynchronous mode.
10
)
BIST Operation and Reporting
The CY7C924ADX HOTLink Transceiver incorporates the same
Built-In Self-Test (BIST) capability used with the HOTLink
CY7B923/ CY7B933 and HOTLink II CYP(V)15G0x0x families.
This link diagnostic uses a Linear Feedback Shift Register
(LFSR) to generate a 511-character repeating sequence that is
compared, character-for-character, at the receiver.
BIST mode is intended to check the entire high-speed serial link
at full link-speed, without the use of specialized and expensive
test equipment. The complete sequence of characters used in
BIST are documented in the HOTLink Built-In Self-Test appli-
cation note.
BIST Enable Inputs
There are separate BIST enable inputs for the transmit and
receive paths of the CY7C924ADX. These inputs are both active
LOW; i.e., BIST is enabled in its respective section of the device
when the BIST enable input is determined to be at a logic-0 level.
Both BIST enable inputs are asynchronous; i.e., they are
synchronized inside the CY7C924ADX to the internal state
machines.
BIST Transmit Path
The transmit path operation with BIST is controlled by the
TXBISTEN* input and overrides most other inputs (see
Figure
and TXBISTEN* is recognized internally, all reads from the
Transmit FIFO are suspended and the BIST generator is enabled
to sequence out the 511 character repeating BIST sequence. If
the Transmit Control State Machine was in the middle of an
atomic operation (e.g., sending an extended command) the Data
Character associated with the Special Character code is trans-
mitted prior to recognition of the TXBISTEN* signal and
suspension of FIFO data processing. If the recognition occurs in
the middle of a data field, the following data is not transmitted at
that time, but remains in the Transmit FIFO. Once the
TXBISTEN* signal is removed, the data in the Transmit FIFO is
again available for transmission. To ensure proper data handling
at the destination, the transmit host controller should either use
TXHALT* or TXSTOP* to segment transmission of data at
specific boundaries, or allow the Transmit FIFO to completely
empty before enabling BIST.
With transmit BIST enabled, the Transmit FIFO remains
available for loading of data. It may be written up to its normal
maximum limit while the BIST operation takes place. To allow
removal of stale data from the Transmit FIFO, it may also be
reset during a BIST operation. The reset operation proceeds as
documented, with the exception of the information presented on
the TXEMPTY* FIFO status flag. Since this flag is used to
present BIST loop status, it continues to reflect the state of the
transmit BIST loop status until TXBISTEN* is no longer recog-
nized internally. The completion of the reset operation may still
be monitored through the TXFULL* FIFO status flag.
8). When the Transmit FIFO is enabled (not bypassed)
CY7C924ADX
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