DP83848IVV/NOPB National Semiconductor, DP83848IVV/NOPB Datasheet - Page 57

• Manufacturer Part Number: DP83848IVV/NOPB
• Description: IC TXRX ETHERNET PHYTER 48-LQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848IVV/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: POEPHYTEREV-I - BOARD EVAL LM5072, DP83848IPOEPHYTEREV-E - BOARD EVAL LM5072, DP83848IDP83848I-POE-EK - BOARD EVALUATION DP83848IDP83848I-MAU-EK - BOARD EVALUATION DP83848I
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83848IVV; *DP83848IVV/NOPB; DP83848IVV; DP83848IVVNOPB; DP83848IVVNOPB; DP83848IVVNOPBTR; DP83848IVVNOPBTR

7.2.9 PHY Control Register (PHYCR)
Bit
15
14
13
12
11
10
9
8
7
BIST_STATUS
BP_STRETCH
FORCE_MDIX
BIST_START
PAUSE_RX
PAUSE_TX
MDIX_EN
Bit Name
BIST_FE
PSR_15
Table 29. PHY Control Register (PHYCR), address 0x19
Strap, RW
0, RW/SC
0, LL/RO
Default
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation En-
able bit in the BMCR register to be set. If Auto-Negotiation is not
enabled, Auto-MDIX should be disabled as well.
Force MDIX:
1 = Force MDI pairs to cross.
0 = Normal operation.
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-
est Common Denominator is a full duplex technology.
Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High-
est Common Denominator is a full duplex technology.
BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the
CDCTRL1 register.
BIST Start:
1 = BIST start.
0 = BIST stop.
Bypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the in-
ternal value.
1 = Bypass LED stretching.
0 = Normal operation.
(Receive on TPTD pair, Transmit on TPRD pair)
57
Description
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