PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet - Page 35

• Manufacturer Part Number: PIC12F683-E/P
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-E/P

• A/d Inputs: 4 Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Serial Interface: None
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 4-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register.
REGISTER 4-4:
4.2.3
The Ultra Low-Power Wake-up (ULPWU) on GP0
allows a slow falling voltage to generate an interrupt-
on-change on GP0 without excess current consump-
tion. The mode is selected by setting the ULPWUE bit
(PCON<5>). This enables a small current sink which
can be used to discharge a capacitor on GP0.
To use this feature, the GP0 pin is configured to output
‘1’ to charge the capacitor, interrupt-on-change for GP0
is enabled and GP0 is configured as an input. The
ULPWUE bit is set to begin the discharge and a SLEEP
instruction is performed. When the voltage on GP0
drops below V
cause the device to wake-up. Depending on the state of
the GIE bit (INTCON<7>), the device will either jump to
the interrupt vector (0004h) or execute the next instruc-
tion when the interrupt event occurs. See Section 4.2.2
“Interrupt-on-change” and Section 12.4.3 “GPIO
Interrupt” for more information.
 2004 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
ULTRA LOW-POWER WAKE-UP
IL
, an interrupt will be generated which will
IOC – INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Legend:
R = Readable bit
- n = Value at POR
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be
U-0
—
2: IOC<5:4> reads ‘1’ in XT, LP and HS modes.
recognized.
U-0
—
R/W-0
IOC5
Preliminary
W = Writable bit
‘1’ = Bit is set
R/W-0
IOC4
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOD
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
This feature provides a low-power technique for period-
ically waking up the device from Sleep. The time-out is
dependent on the discharge time of the RC circuit
on GP0. See Example 4-2 for initializing the Ultra
Low-Power Wake-up module.
The series resistor provides overcurrent protection for the
GP0 pin and can allow for software calibration of the time-
out (see Figure 4-1). A timer can be used to measure the
charge time and discharge time of the capacitor. The
charge time can then be adjusted to provide the desired
interrupt delay. This technique will compensate for the
affects of temperature, voltage and component accuracy.
The Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low-Voltage
Detect or temperature sensor.
Note:
Note:
Any read or write of GPIO. This will end the
mismatch condition, then
Clear the flag bit GPIF.
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
IOC3
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
For more information, refer to the Applica-
tion Note AN879, “Using the Microchip
Ultra
(DS00879).
Low-Power
R/W-0
IOC2
PIC12F683
x = Bit is unknown
R/W-0
Wake-up
IOC1
DS41211B-page 33
R/W-0
Module”
IOC0
bit 0