PIC16C711-04/P Microchip Technology Inc., PIC16C711-04/P Datasheet - Page 15

• Manufacturer Part Number: PIC16C711-04/P
• Description: 18 PIN, 1.75 KB OTP, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C711-04/P

• A/d Inputs: 4-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 13
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 4-2:
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
1997 Microchip Technology Inc.
Bank 0
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
ADRES
ADCON0
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
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—
—
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—
—
—
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
ADCS1
IRP
Bit 7
GIE
—
—
—
(4)
ADCS0
RP1
PEIE
ADIF
Bit 6
—
—
(4)
CHS2
Bit 5
T0IE
RP0
—
—
—
PORTA Data Latch when written: PORTA pins when read
Write Buffer for the upper 5 bits of the Program Counter
CHS1
INTE
Bit 4
TO
—
CHS0
RBIE
Bit 3
PD
—
GO/DONE
Bit 2
T0IF
—
Z
INTF
Bit 1
DC
—
—
PIC16C71X
ADON
RBIF
Bit 0
—
C
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---x 0000 ---u 0000
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
BOR, PER
Value on:
POR,
DS30272A-page 15
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other resets
Value on all
(3)
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