KSZ8721SL TR Micrel Inc, KSZ8721SL TR Datasheet - Page 7

• Manufacturer Part Number: KSZ8721SL TR
• Description: IC TXRX PHY 10/100 3.3V 48SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721SL TR

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1630 - BOARD EVALUATION FOR KSZ8721SL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1031-2

Micrel, Inc.
Pin Description
June 2009
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
PCS_LPBK
RXER/ISO
RMII_BTB
Pin Name
PHYAD2
PHYAD3
PHYAD4
REFCLK
CRSDV/
PHYAD
VDDIO
RXDV/
RXD3/
RXD2/
RXD1/
RXD0/
VDDC
MDIO
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
COL/
CRS/
MDC
GND
GND
TXC/
GND
RXC
RMII
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Gnd
Gnd
Gnd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
I/O
O
P
P
I
(1)
Pin Function
Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K
pull-up resistor.
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See “Strapping
Options” section for details.
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See
“Circuit Design Ref. for Power Supply" section for details.
Ground.
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping
Options” section for details.
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section
for details.
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock
interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave XO pin unconnected.
MII Collision Detect Output.
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping
Options” section for details.
MII Carrier Sense Output.
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when
RMII mode is selected. See “Strapping Options” section for details.
Ground.
MII Clock Input. This pin is synchronous to the MDIO.
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Transmit Error Input.
MII Transmit Enable Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
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M9999-062509-1.3
KS8721BL/SL