KSZ8721SL TR Micrel Inc, KSZ8721SL TR Datasheet - Page 9

• Manufacturer Part Number: KSZ8721SL TR
• Description: IC TXRX PHY 10/100 3.3V 48SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721SL TR

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1630 - BOARD EVALUATION FOR KSZ8721SL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1031-2

Strapping Options
Notes:
1. Strap-in is latched during power-up or reset.
2. Ipu = Input w/ internal pull-up.
May 2004
KS8721BL/SL
Pin Number
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
6,5,
4,3
25
11
21
22
27
28
29
30
9
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
NWAYEN/
Pin Name
RMII_BTB
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED1
LED2
LED3
INT#
CRS
PD#
(1)
Type
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(2)
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
(default) = Full-duplex. If Duplex is pulled up during reset, this pin is also latched as
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
9
M9999-051704
Micrel