MAX5062AASA Maxim Integrated Products, MAX5062AASA Datasheet - Page 12

• Manufacturer Part Number: MAX5062AASA
• Description: MOSFET & Power Driver ICs 125V 2A Half-Bridge MOSFET Driver
• Manufacturer: Maxim Integrated Products
• Type: High Side/Low Sider

Specifications of MAX5062AASA

• Rise Time: 65 ns
• Fall Time: 65 ns
• Supply Voltage (min): 8 V
• Supply Current: 3 mA
• Maximum Power Dissipation: 470.6 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Number Of Outputs: 2

Pay extra attention to bypassing and grounding the
MAX5062/MAX5063/MAX5064. Peak supply and output
currents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
ground return path. Any series inductance in the V
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX5062/
MAX5063/MAX5064 with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel as
close to the device as possible to bypass V
(MAX5062/MAX5063) or PGND (MAX5064). Use a
ground plane to minimize ground return resistance and
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < t
12
A)
B)
PWM
PWM
______________________________________________________________________________________
IN
IN
Supply Bypassing and Grounding
BBM DELAY
BBM DELAY
EXTERNAL
EXTERNAL
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
MAX5062A/MAX5062C/MAX5063A/MAX5063C/MAX5064
Applications Information
V
V
DD
DD
INH
INL
INH
INL
DH
DH
HS
HS
DL
DL
V
V
IN
IN
DD
N
N
N
N
to GND
DD
,
V
V
OUT
OUT
series inductance. Place the external MOSFET as close
as possible to the MAX5062/MAX5063/MAX5064 to fur-
ther minimize board inductance and AC path resis-
tance. For the MAX5064_ the low-power logic ground
(AGND) is separated from the high-power driver return
(PGND). Apply the logic-input signal between IN_ to
AGND and connect the load (MOSFET gate) between
DL and PGND.
Power dissipation in the MAX5062/MAX5063/MAX5064
is primarily due to power loss in the internal boost
diode and the nMOS and pMOS FETS.
For capacitive loads, the total power dissipation for the
device is:
P
D
=
C)
⎛
⎝
PW-MIN
C
L
DL
DH
PWM
×
)
V
IN
DD
2
×
f
SW
⎞
⎠ +
(
t
I
DMIN-DH-L
DDO
t
DMIN-DL-H
Power Dissipation
+
BBM DELAY
EXTERNAL
I
BSTO
)
POTENTIAL
OVERLAP TIME
×
V
DD