MAX5078AATT-T Maxim Integrated Products, MAX5078AATT-T Datasheet - Page 8

• Manufacturer Part Number: MAX5078AATT-T
• Description: MOSFET & Power Driver ICs 4A 20ns MOSFET Driver
• Manufacturer: Maxim Integrated Products
• Type: Low Sider

Specifications of MAX5078AATT-T

• Rise Time: 85 ns
• Fall Time: 75 ns
• Supply Voltage (min): 4 V
• Supply Current: 0.04 mA
• Maximum Power Dissipation: 1454 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Maximum Turn-off Delay Time: 35 ns
• Maximum Turn-on Delay Time: 35 ns
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 1
• Number Of Outputs: 1

The MAX5078A/MAX5078B have internal undervoltage
lockout (UVLO) for V
threshold, OUT is pulled low independent of the state of
the inputs. The undervoltage lockout is typically 3.5V with
200mV typical hysteresis to avoid chattering. When V
rises above the UVLO threshold, the output goes high or
low depending upon the logic-input levels. Bypass V
using a low-ESR ceramic capacitor for proper operation
(see the Applications Information section).
The MAX5078A has CMOS logic inputs while the
MAX5078B has TTL-compatible logic inputs. The logic
inputs are protected against the voltage spikes up to
18V, regardless of the V
logic inputs have 300mV and 0.1 x V
respectively, to avoid double pulsing during transition.
The low 2.5pF input capacitance reduces loading and
increases switching speed.
The logic inputs are high impedance and must not be left
floating. If the inputs are left open, OUT can go to an
undefined state as soon as V
threshold. Therefore, the PWM output from the controller
must assume proper state when powering up the device.
The MAX5078A/MAX5078B have two logic inputs, provid-
ing greater flexibility in controlling the MOSFET. Use IN+
for noninverting logic and IN- for inverting logic operation.
Connect IN+ to V
Alternatively, the unused input can be used as an
ON/OFF function. Use IN+ for active-low shutdown logic
and IN- for active-high shutdown logic (see
Table
4A, 20ns, MOSFET Driver
8
_______________________________________________________________________________________
PIN
2, 3
—
1 for all possible input combinations.
1
4
5
6
V
DD
NAME
Undervoltage Lockout (UVLO)
GND
OUT
V
IN+
IN-
EP
DD
DD
DD
Detailed Description
. When V
and IN- to GND, if not used.
DD
Inverting Logic-Input Terminal. Connect to GND when not used.
Ground
Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors.
Driver Output. Sources or sinks current to turn the external MOSFET on or off.
Noninverting Logic-Input Terminal. Connect to V
Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical
ground connection.
voltage. The TTL and CMOS
DD
DD
rises above the UVLO
is below the UVLO
Logic Inputs
DD
Figure
hysteresis,
3). See
DD
DD
The MAX5078A/MAX5078B have low R
and n-channel devices (totem pole) in the output stage
for the fast turn-on/turn-off, high-gate-charge switching
MOSFETs. The peak source or sink current is typically
4A. The output voltage (V
V
The driver R
higher source-/sink-current capability and faster switch-
ing speeds. The propagation delays from the noninvert-
ing and inverting logic inputs to OUT are matched to 2ns
typically. The break-before-make logic avoids any cross-
conduction between the internal p- and n-channel
devices, and eliminates shoot-through, thus reducing the
quiescent supply current.
The driver’s R
tance (L
and gate capacitance (C
circuit with a second-order characteristic equation. The
series RLC circuit has an undamped natural frequency
(
The damping ratio needs to be greater than 0.5 (ideally
1) to avoid ringing. Add a small resistor (R
series with the gate when driving a very low gate-
charge MOSFET, or when the driver is placed away
from the MOSFET.
DD
0
) and a damping ratio ( ) where:
when in high state and is ground when in low state.
FUNCTION
DD
P
), trace inductance (L
when not used.
DS(ON)
DS(ON)
0
Applications Information
2
(
is lower at higher V
L
P
(R
(
L
ON
R
P
OUT
L
ON
S
), internal bond/lead induc-
C
L
) is approximately equal to
S
1
G
G
L
S
Pin Description
) form a series RLC
G
RLC Series Circuit
), gate inductance (L
L
)
G
)
C
Driver Output
DS(ON)
G
DD
resulting in
p-channel
GATE
) in
G
),