ispPAC-POWR6AT6-01S32I Lattice, ispPAC-POWR6AT6-01S32I Datasheet - Page 23

• Manufacturer Part Number: ispPAC-POWR6AT6-01S32I
• Description: Supervisory Circuits Prec Prog Pwr Supply Seq Mon IND
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR6AT6-01S32I

• Mounting Style: SMD/SMT
• Package / Case: QFNS-32
• Applications: Power Supply Controller/Monitor
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-20. Closed-Loop Trim Lock (CLTLOCK/SMBA) Signal Processing Logic Flow Diagram
The ispPAC-POWR6AT6 contains trim detection processing circuitry to signal when closed-loop trimming is com-
plete for selected trim output pins. This signal is output on the closed-loop control output pin (CLTLOCK/SMBA)
which has a open drain output and is normally asserted low (pull down). When all closed-loop trim output pins
reach a completion or trim “locked” condition, the CLTLOCK/SMBA output pin pulls low. Afterwards, the CLTLOCK/
SMBA pin also indicates when a trimming fault exists by de-asserting (going high). Finally, the CLTLOCK/SMBA pin
can be configured to work in conjunction with the SMBus Alert protocol to signal when trim lock has been achieved
or lost (see the section on SMBus Alert for details).
Figure 3-21 shows a simplified diagram of how the state of the CLTLOCK/SMBA output pin is generated. After
closed loop trimming is enabled, the CLTLOCK/SMBA signal processing logic examines the output result from the
ADC going to each TrimCell at the end of each trim update cycle. If it is determined that a trim lock condition exists
for that trim output pin, the trim lock signal is asserted. The status of an individual trim output can be read via the
I
automatically indicate a trim locked condition.
Figure 3-21. Closed-Loop Trim Lock Output Pin (CLTLOCK/SMBA) Functionality
Next, an individual lock signal is OR'd with an E
ing bits, one for each possible trim output pin. When set, masking bits effectively override the lock determination for
a particular trim output pin. The default setting for all mask bits is cleared (not set). Changes to the device configu-
ration mask bits can be made using PAC-Designer.
2
C closed loop trim register (refer to Figure 3-15). Trim output pins not selected for closed-loop trim operation will
I
Trim1-6 (6-bits); 1 = Locked
2
C CLTLOCK/SMBA Status:
1
6
lock = 1
5
E
Mask CLTLOCK/SMBA
same as
Trim1-5
2
below
Configuration
Determine “Lock”
status of Trim-n
measurement
Vmon-n ADC
Trim6
5
Start
Runs when CLTENb
pin is asserted.
2
CMOS mask bit specific to that trim output pin. There are six mask-
Locked?
Trim
3-23
No
Yes
SMBus
Control
Logic
I
2
C/
Clear “Lock” result
Set “Lock” result
for Trim-n
for Trim-n
ispPAC-POWR6AT6 Data Sheet
E
Default = 0
0
1
2
Configuration
CLTLOCK/SMBA