MAX6897PAZT+T Maxim Integrated Products, MAX6897PAZT+T Datasheet - Page 7

• Manufacturer Part Number: MAX6897PAZT+T
• Description: Supervisory Circuits Adjustable Sequencer/Supervisor
• Manufacturer: Maxim Integrated Products

Specifications of MAX6897PAZT+T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Connect the center point of a resistive divider to IN to
monitor external voltages (see R1 and R2 of the Typical
Operating Circuit ). IN has a rising threshold of V
0.5V and a falling threshold of 0.495V (5mV hysteresis).
When V
ENABLE is low) OUT goes high (OUT goes low) after
the programmed t
0.495V, OUT goes low (OUT goes high) after a 16µs
delay. IN has a maximum input current of 15nA so
large-value resistors are permitted without adding sig-
nificant error to the resistive divider.
When V
low), the internal 250nA current source begins charging
an external capacitor connected from CDELAY to GND.
When the voltage at CDELAY reaches 1V, the output
Figure 2. MAX6895A/MAX6897A Timing Diagram
ENABLE
V
OUT
CC
IN
IN
IN
rises above V
rises above V
_______________________________________________________________________________________
DELAY
Adjustable Delay (CDELAY)
V
UVLO
TH
period. When V
TH
with ENABLE high (ENABLE
and ENABLE is high (or
t
PROPA
Monitor Input (IN)
Sequencing/Supervisory Circuits
IN
falls below
TH
t
DL
=
V
TH
Ultra-Small, Adjustable
asserts (OUT goes high or OUT goes low). When the
output asserts, C
Adjust the delay (t
V
high (OUT going low) according to the equation:
where C
to GND.
For adjustable delay devices (A version), when V
0.5V and ENABLE goes from low to high (ENABLE
goes from high to low) the output asserts after a t
period. For nonadjustable delay devices (P version)
there is a 1µs propagation delay from when the enable
input is asserted to when the output asserts. Figures 2
through 5 show the timing diagrams for the adjustable
and fixed delay versions, respectively.
TH
(with ENABLE high or ENABLE low) to OUT going
t
V
DELAY
TH
CDELAY
t
DELAY
= C
is the external capacitor from CDELAY
CDELAY
DELAY
CDELAY
t
OFF
t < t
PROPA
) from when V
is immediately discharged.
x 4.0 x 10
t > t
PW
6
t
PROPA
+ 40µs
IN
rises above
DELAY
IN
>
7