CAT1640WI-45-G ON Semiconductor, CAT1640WI-45-G Datasheet - Page 12

• Manufacturer Part Number: CAT1640WI-45-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1640WI-45-G

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Power-up Reset Delay (typ): 270 ms
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Immediate/Current Address Read
The CAT1640 and CAT1641 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=8,192. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1640 and
CAT1641 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1640 and CAT1641
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1640 and CAT1641 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 11. Selective Read Timing
*=Don’t Care Bit
CAT1640, CAT1641
Doc. No. MD-3012, Rev. D
Figure 12. Sequential Read Timing
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
MASTER
SDA LINE
MASTER
S
S
A
R
T
T
ADDRESS
ADDRESS
SLAVE
SLAVE
C
A
K
A
C
K
* * *
DATA n
A 15 –A 8
BYTE ADDRESS
A
C
K
A
C
K
DATA n+1
A 7 –A 0
12
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1640 and CAT1641 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1640
and CAT1641 address bits so that the entire memory
array can be read during one operation.
A
C
K
A
C
K
S
S
A
R
T
T
DATA n+2
ADDRESS
SLAVE
C
A
K
Characteristics subject to change without notice.
A
C
K
DATA
DATA n+x
© 2009 SCILLC. All rights reserved.
N
O
A
C
K
O
N
A
C
K
S
O
P
P
T
O
S
T
P
P