MC145572AACR2 Freescale Semiconductor, MC145572AACR2 Datasheet - Page 185

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MC145572AACR2

Manufacturer Part Number
MC145572AACR2
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145572AACR2

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
10.10.3
MOTOROLA
SFAX/SFAR Output Timing in IDL2 (Master or Slave) Short Frame
Mode
NOTES:
Ref. No.
1. See Section 10.7 for FSX jitter requirements and specifications.
2. SFAX and SFAR must occur every 96 FSX 8 kHz frames.
3. FAX and SFAR are one DCL clock pulse wide and occur on the next DCL clock pulse after FSX or FSR is asserted.
102
103
104
105
FSX Period
SFAX Period
Delay From the Rising Edge of DCL to the Rising Edge of
FSAR or FSAX
Delay From the Rising Edge of DCL to the Rising Edge of
FSAR or FSAX
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Parameter
MC145572
12.0
Min
125
Max
30
30
Unit
ms
ns
ns
s
10–23
Note
1
2
3

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