MC145572PBR2 Freescale Semiconductor, MC145572PBR2 Datasheet - Page 251

• Manufacturer Part Number: MC145572PBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
act, 6–5
act Bit, 4–13
Activation, 4–6, 4–8, 4–29, 5–30, 6–1, 6–6, 8–12,
Activation Timer, 4–26
Activation, Deactivation
ANSI T1.601–1992, 1–2
Applications, 2–1, 6–6, F–1
Baud Clock, 4–29
Byte Register, 5–9
Clock Reference, 3–12
Command/Indicate Channel, 8–11
Configurations, 5–4
Crystal, 3–12, 3–13, B–2, C–2
Verified act, 4–13
BR11, 4–25
BR12, 4–26
Customer Enable, 4–8
NR1, 4–6
Activation, 4–8
NR2, 4–8
LAN Server, F–5, F–6
NT1, F–2
Pair Gain Application, Central Office Terminal,
Pair Gain Application, Remote Terminal, 2–3
Repeater Applications, 6–6
Smart NT1, F–4
Typical ISDN Applications, 2–2
U–Terminal, F–3
Crystal Characterization, H–1, H–2
Crystal Oscillator and Phase Locked Loop (PLL)
9–1, 9–2, 9–4, 9–6
2–3
Pins, 3–12
A
B
C
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MC145572
D Channel, 4–7, 4–35, 5–20, 9–13, 10–15, 10–17,
dea, 6–5
dea Bit, 4–14
Deactivation, 4–8, 6–1, 8–12
Digital Loop Carrier Systems, 4–20
Echo Canceller, 4–27
eoc, 4–20, 5–7, 7–2, 9–1, 9–2, 9–4
ETSI ETR 080, 1–2
Eye, D–1
Eye Data, 4–29, 10–31
febe, 4–24, 9–11
FIFOs, 1–2, 5–30
D Channel Interrupt, 4–7
D Channel Port, 5–20
Select DCH Access, 4–25
Verified dea, 4–14
LT Deactivation, 6–5
NT Deactivation, 6–5
Superframe Update Disable, 4–8
BR13, 4–27
Automatic eoc Processor Mode (b7 = 0, b6 =
crc Corrupt, 4–20
eoc Control 1:0, 4–21
eoc Processor Functions, 4–22
eoc Trinal–Check Mode (b7, b6 = 1,0), 4–22
R6, 4–10
Return to Normal, 4–6
BR4, 4–14
febe and nebe Bits, 7–3
Received febe, 4–13
Frame Sync to U–Interface Propagation Delays,
10–19
Don’t Care), 4–22
5–30
D
E
F
INDEX
Index–1