PSB3186FV14XP Lantiq, PSB3186FV14XP Datasheet - Page 8

• Manufacturer Part Number: PSB3186FV14XP
• Manufacturer: Lantiq

Specifications of PSB3186FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

List of Figures
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Data Sheet
Logic Symbol of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Applications of the ISAC-SX TE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Configuration of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional Block Diagram of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . 26
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 32
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 40
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 41
Data Delay between IOM-2 and S/T Interface . . . . . . . . . . . . . . . . . . . 44
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation 45
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 46
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 46
Connection of Line Transformers and Power Supply to the
ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 49
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 50
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock System of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Phase Relationships of ISAC-SX TE Clock Signals . . . . . . . . . . . . . . 55
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
State Transition Diagram of Unconditional Transitions (TE) . . . . . . . . 61
Example of Activation/Deactivation Initiated by the Terminal . . . . . . . 67
IOM Ò -2 Frame Structure in Terminal Mode . . . . . . . . . . . . . . . . . . . . 69
Architecture of the IOM Handler (Example Configuration). . . . . . . . . . 71
Data Access via CDAx1 and CDAx2 Register Pairs . . . . . . . . . . . . . . 73
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 74
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 75
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 76
8
ISAC-SX TE
PSB 3186
2003-01-30
Page