CLC012AJE National Semiconductor, CLC012AJE Datasheet - Page 8

• Manufacturer Part Number: CLC012AJE
• Manufacturer: National Semiconductor

Specifications of CLC012AJE

• Lead Free Status / Rohs Status: Not Compliant

www.national.com
Operation
The CLC012 Adaptive Cable Equalizer provides a complete
solution for equalizing high-bit-rate digital data transmitted
over long transmission lines. The following sections furnish
design and application information to assist in completing a
successful design:
For applications assistance in the U.S., call 800-272-9959 to
contact a technical staff member.
• Block diagram explanation of the CLC012
• Recommended standard input and output interface con-
• Common applications for the CLC012
• Measurement, PC layout, and cable emulation boxes
nections
FIGURE 1. CLC012 Equalizer Application Circuit
DI, DI
DO, DO
AEC+,
AEC−
OEM
LOS
MUTE
V
V
CC
EE
Name
10, 11 Negative supply pins (−5.2V
Pin #
1, 2,
8, 9
6, 7
13,
14
12
3
5
4
Pin Definitions
Differential data inputs.
Differential collector data
outputs (ECL compatible).
AEC loop filter pins.
A capacitor connected
between these pins governs
the loop response for the
adaptive equalization loop.
Eye monitor output. The
output of the equalization
filter.
Loss of Signal. (Low when no
signal is present).
Output MUTE. (Active low.)
Loss of Signal (LOS) may be
tied to this pin to inhibit the
output when no signal is
present.
Positive supply pins (ground
or +5V).
or ground).
Description
10014520
8
BLOCK DESCRIPTION
The CLC012 is an adaptive equalizer that reconstructs serial
digital data received from transmission lines such as coaxial
cable or twisted pair. Its transfer function approximates the
reciprocal of the cable loss characteristic. The block diagram
in Figure 2 depicts the main signal conditioning blocks for
equalizing digital data at the receiving end of a cable. The
CLC012 receives baseband differential or single-ended digi-
tal signals at its inputs DI and DI.
The Equalizer block is a two-stage adaptive filter. This filter
is capable of equalizing cable lengths from zero meters to
lengths that require 40 dB of boost at 200 MHz.
The Quantized Feedback Comparator block receives the
differential signals from the equalizer filter block. This block
includes two comparators. The first comparator incorporates
a self-biasing DC restore circuit. This is followed by a second
high-speed comparator with output mute capability. The sec-
ond comparator receives and slices the DC-restored data.
Its outputs DO and DO are taken from the collectors of the
output transistors. MUTE latches DO and DO when a TTL
logic low level is applied.
The Adaptive Servo Control block produces the signal for
controlling the filter block, and outputs a voltage proportional
to cable length. It receives differential signals from the output
of the filter block and from the quantized-feedback compara-
tor (QFBC) to develop the control signal. The servo loop
response is controlled by an external capacitor placed
across the AEC+ and AEC− pins. Its output voltage, as
measured differentially across AEC+ and AEC−, is roughly
proportional to the length of the transmission line. For
Belden 8281 coaxial cable this differential voltage is about
1.5 mV/meter. Once this voltage exceeds 500 mV, no addi-
tional equalization is provided.
The Loss of Signal (LOS) block monitors the signal power
out of the equalizing filter and compares it to an internal
reference to determine if a valid signal is present. A CMOS
high output indicates that data is present. The output of LOS
can be connected to the MUTE input to automatically latch
the outputs (DO and DO), preventing random transitions
when no data is present.
The Output Eye Monitor (OEM) provides a single-ended
buffered output for observing the equalized eye pattern. The
OEM output is a low impedance high-speed voltage driver
capable of driving an AC-coupled 100Ω load.
FIGURE 2. CLC012 Block Diagram
10014521