GS8322Z36B-166I GSI TECHNOLOGY, GS8322Z36B-166I Datasheet - Page 16

• Manufacturer Part Number: GS8322Z36B-166I
• Manufacturer: GSI TECHNOLOGY

Specifications of GS8322Z36B-166I

• Density: 36Mb
• Access Time (max): 8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 125MHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 20b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 190mA
• Operating Supply Voltage (min): 2.3/3V
• Operating Supply Voltage (max): 2.7/3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Number Of Words: 1M
• Lead Free Status / Rohs Status: Not Compliant

Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
FLXDrive™
The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions
Note:
There are pull-up devices on the ZQ and FT pins and a pull-down devices on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.07 4/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Burst Counter Sequences
FLXDrive Output Impedance Control
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
Table 1:
11
01
10
00
Name
10
11
00
01
LBO
Pin
ZQ
ZZ
FT
11
00
01
10
H or NC
H or NC
L or NC
State
H
H
L
L
L
16/40
High Drive (Low Impedance)
Low Drive (High Impedance)
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
Standby, I
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
Flow Through
Linear Burst
Function
2nd address
3rd address
4th address
1st address
Pipeline
Active
DD
= I
SB
A[1:0] A[1:0] A[1:0] A[1:0]
01
00
10
11
Table 2:
01
00
11
10
10
11
00
01
© 2002, GSI Technology
11
10
01
00
BPR 1999.05.18