LTC2934ITS8-1#PBF Linear Technology, LTC2934ITS8-1#PBF Datasheet - Page 7

• Manufacturer Part Number: LTC2934ITS8-1#PBF
• Manufacturer: Linear Technology

Specifications of LTC2934ITS8-1#PBF

• Lead Free Status / Rohs Status: Compliant

APPLICATIONS INFORMATION
VOLTAGE MONITORING
Unmanaged power can cause various system problems.
At power-up, voltage fl uctuation around critical thresholds
can cause improper system or processor initialization.
The LTC2934 provides power management capabilities
for the system power-up phase. The supervisory device
issues a system reset after the monitored voltage has
stabilized. Built-in hysteresis and fi ltering ensures that
fl uctuations due to load transients or supply noise do
not cause chattering of the status outputs. Comparator
undervoltage glitch immunity is shown in the Typical
Performance Characteristics section. The curve dem-
onstrates the transient amplitude and width required to
switch the comparators.
Because many batteries exhibit large series resistance,
load currents can cause signifi cant voltage drops. The
low DC current draw of the LTC2934 (at any input volt-
age) does not add to the loading problem. When voltage
is initially applied to V
is enough voltage to turn on the pull-down devices (1V
maximum).
If the monitored supply voltage falls to the power-fail
threshold, the built-in power-fail comparator pulls PFO low.
PFO remains low until the PFI input rises above 0.4V plus
2.5% hysteresis. PFO is typically used to signal preparation
for controlled shutdown. For example, the PFO output may
be connected to a processor nonmaskable interrupt. Upon
interrupt, the processor begins shutdown procedures such
as supply sequencing and/or storage/erasure of system
state in nonvolatile memory.
If the monitored voltage drops below the reset threshold,
RST pulls low until the ADJ input rises above 0.4V plus
5% hysteresis. This may occur through battery charging
or replacement. An internal reset timer delays the return
of the RST output to a high state to provide settling and
initialization time. The RST output is typically connected
to processor reset input.
Few, if any external components are necessary for reliable
operation. However, a decoupling capacitor between V
and ground is recommended (0.01μF minimum).
CC
, RST and PFO pull low once there
CC
Threshold Confi guration
The LTC2934 monitors voltage applied to its inputs PFI and
ADJ. A resistive divider connected between a monitored
voltage and ground is used to bias the inputs. Figure 1
demonstrates how the monitor inputs can be made de-
pendent upon a single voltage (V1). Only three resistors
are required. To calculate their values, specify desired
falling power fail (V
> V
The solution for R1, R2, and R3 provides three equations
and three unknowns. Maximum resistor size is governed
by maximum input leakage current. For the LTC2934, the
maximum input leakage current over temperature is 1nA.
For a maximum error of 1% due to both input currents,
the resistor divider current should be 100 times the sum
of the leakage currents, or 0.2μA. At the reset threshold,
V1 = 1.62V, so R
The falling monitor thresholds (V
The closest 1% value is 1.87M. R2 can be determined
from:
V
R
R
R
R
R
PF
SUM
. For example:
1
2
2 130
Figure 1. Confi guration for Single Voltage Monitoring
=
= 1.72V, V
=
=
= R1 + R2 + R3
V
V
V1
TH
TH
k k
V
•
•
V
PF
R
R
SUM
R
R
SUM
SUM
= 1.62V
R3
R2
R1
PF
= V1/0.2μA = 8.1M where:
) and reset voltages (V
=
–
R
0 4
1
.
1 72
=
V
.
ADJ
PFI
• .
TH
0 4
8 1
.
V
) are 0.4 volts, so:
LTC2934
1 62
V
M
.
LTC2934
• .
8 1
=
V
2934 F01
M
1 88
R
.
) with V
−
1 87
M
.
7
2934f
M
PF