ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 43

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

Watchdog Timer
Register Description
Watchdog Timer Control
Register – WDTCR
1006F–AVR–06/07
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 19. See characterization data for typical values at other V
Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the ATtiny11/12 resets and executes from the reset vector. For
timing details on the Watchdog reset, refer to page 28.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be
followed when the watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 24. Watchdog Timer
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and will always read as zero.
• Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not
be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to
the description of the WDE bit for a watchdog disable procedure.
• Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can be cleared only when the
WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure
must be followed:
Bit
$21
Read/Write
Initial Value
Oscillator
R
7
0
-
350 kHz at V
110 kHz at V
1 MHz at V
R
6
0
-
CC
CC
CC
= 5V
= 3V
= 2V
R
5
0
-
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
R/W
ATtiny11/12
CC
1
0
levels. The WDR –
WDP0
R/W
0
0
WDTCR
43