ATTINY12L-4SU Atmel, ATTINY12L-4SU Datasheet - Page 9

• Manufacturer Part Number: ATTINY12L-4SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 3V 4MHZ
• Manufacturer: Atmel

Specifications of ATTINY12L-4SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Package: 8SOIC EIAJ
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: SPI
• Operating Temperature: -40 to 85 °C
• Lead Free Status / Rohs Status: Details

Status Register
Status Register – SREG
1006F–AVR–06/07
The AVR status register (SREG) at I/O space location $3F is defined as:
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-
pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the
Instruction Set description for detailed information.
• Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the
Instruction Set description for detailed information.
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-
tion Set description for detailed information.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Bit
$3F
Read/Write
Initial Value
R/W
7
0
I
R/W
T
6
0
R/W
H
5
0
R/W
S
4
0
R/W
3
V
0
R/W
2
N
0
ATtiny11/12
R/W
Z
1
0
R/W
C
0
0
SREG
9