M28W640FSU70ZA6 Micron Technology Inc, M28W640FSU70ZA6 Datasheet - Page 27

• Manufacturer Part Number: M28W640FSU70ZA6
• Manufacturer: Micron Technology Inc

Specifications of M28W640FSU70ZA6

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Address Bus: 22b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

M28WxxxFS, M28WxxxFSU
7
7.1
7.2
Status Register
The Status Register provides information on the current or previous Program or Erase
operation. The various bits convey information and errors on the operation. To read the
Status register the Read Status Register command can be issued, refer to Read Status
Register Command section. To output the contents, the Status Register is latched on the
falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable
or Output Enable returns to V
update the latched data.
Bus Read operations from any address always read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 9
Program/Erase Controller Status (Bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the
Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase
Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, V
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of
the Program/Erase Suspend command being issued therefore the memory may still
complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
in conjunction with the following text descriptions.
PP
Status and Block Lock Status bits should be tested for errors.
IH
. Either Chip Enable or Output Enable must be toggled to
Table 9: Status Register
Status Register
bits. Refer to
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