MAX5981AETE+ Maxim Integrated Products, MAX5981AETE+ Datasheet - Page 8

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MAX5981AETE+

Manufacturer Part Number
MAX5981AETE+
Description
Power Switch ICs - POE / LAN IEEE 802.3af/at PDIC Controller
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX5981AETE+

Lead Free Status / Rohs Status
 Details
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with
8
PIN
______________________________________________________________________________________
11
12
13
14
15
16
––
NAME
2EC
CLS
LED
ULP
WK
SL
EP
2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC
when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current
sink is enabled after the isolation MOSFET is fully on until V
latched when powered by a Type 2 PSE until V
when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not
latched if asserted by WAD. The 2EC current sink is turned off when the device is in sleep mode.
Classification Resistor Input. Connect a resistor (R
current. See the classification current specifications in the Electrical Characteristics table to find the resistor
value for a particular PD classification.
LED Driver Output. During sleep mode, LED sources a periodic current (I
set by R
Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode (V
0.75V). An external resistor (R
Wake Mode Enable Input. WK has an internal 2.5kI pullup resistor to the internal 5V bias rail. A falling
edge on WK brings the device out of sleep mode and into the normal operating mode (wake mode).
Ultra-Low-Power Enable Input (in Sleep Mode). ULP has an internal 50kI pullup resistor to the internal
5V bias rail. A falling edge on SL while ULP is asserted low enables ultra-low-power mode. When ultra-
low-power mode is enabled, the power consumption of the device is reduced even lower than normal
sleep while still supporting MPS.
Exposed Pad. Do not use EP as an electrical connection to V
through a resistive path and must be connected to V
the exposed pad to a large copper power plane.
SL
according to the formula I
Integrated Power MOSFET
SL
) connected between SL and V
LED
(in A) = 645.75/(R
FUNCTION
IN
CLS
drops below the reset threshold. 2EC also asserts
) from CLS to V
SS
externally. To optimize power dissipation, solder
Pin Description (continued)
IN
SL
SS
drops below the UVLO threshold. 2EC is
+ 1200).
SS
. EP is internally connected to V
sets the LED current (I
SS
to set the desired classification
LED
). The amplitude of I
SL
must drop below
LED
).
SS
LED
is

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