ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet - Page 39

• Manufacturer Part Number: ADV7321KSTZ
• Description: IC VID ENC 6-12BIT DAC'S 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7321KSTZ

• Applications: EVD, DVD, SD/PS/HDTV
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 8- or 10-bit SD data must be compliant with ITU-R
BT.601/656 in 4:2:2 format. SD data is input on Pins S9 to S0,
with S0 being the LSB. Using 8-bit input format, the data is
input on Pins S9 to S2. The clock input for SD must be input on
CLKIN_A, and the clock input for HD must be input on
CLKIN_B. Synchronization signals are optional. SD syncs are
input on Pins S_VSYNC , S_HSYNC , and S_BLANK . HD syncs
are input on Pins P_VSYNC , P_HSYNC , and P_BLANK .
In simultaneous SD/HD input mode, if the two clock phases
differ by less than 9.25 ns or by more than 27.75 ns, the clock
align bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
clock align bit must be set because the phase difference between
both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
INTERLACED TO
PROGRESSIVE
t
t
Figure 53. Clock Phase with Two Input Clocks
DELAY
DELAY
DECODER
DECODER
DECODER
Figure 52. Simultaneous SD and HD Input
Figure 51. Simultaneous SD and PS Input
MPEG2
YCrCb
HDTV
SDTV
< 9.25ns OR
> 27.75ns
1080i
1035i
720p
OR
OR
YCrCb
CrCb
Y
74.25MHz
27MHz
27MHz
CrCb
Y
27MHz
10
10
10
3
3
10
10
10
3
3
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_HSYNC,
P_BLANK
CLKIN_B
S_VSYNC,
S_HSYNC,
S_BLANK
P_VSYNC,
S_VSYNC,
S_HSYNC,
S_BLANK
CLKIN_A
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
ADV7320/
ADV7321
ADV7320/
ADV7321
Rev. A | Page 39 of 88
PS AT 27 MHZ (DUAL EDGE) OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb PS data can be input at 27 MHz or 54 MHz. The input
data is interleaved onto a single 8-/10-bit bus and is input on
Pins Y9 to Y0. When a 27 MHz clock is supplied, the data is
clocked upon the rising and falling edges of the input clock, and
the clock edge bit [Address 0x01, Bit 1] must be set accordingly.
Table 22 provides an overview of all possible input
configurations. Figure 54, Figure 55, and Figure 56 show the
possible conditions: Cb data on the rising edge, and Y data on
the rising edge.
PIXEL INPUT
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Y9–Y0
Y9–Y0
CLKIN_B
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
DATA
PROGRESSIVE
DECODER
3FF
3FF
INTERLACED
MPEG2
YCrCb
Figure 57. 10-Bit PS at 27 MHz or 54 MHz
3FF
TO
00
00
00
27MHz OR 54MHz
00
00
YCrCb
00
XY
XY
10
XY
3
ADV7320/ADV7321
Cb0
Y0
P_HSYNC,
P_BLANK
CLKIN_A
Y[9:0]
P_VSYNC,
Cb0
ADV7320/
ADV7321
Cb0
Y0
Y0
Cr0
Y1
Cr0
Y1
Cr0
Y1