ADV7301AKST Analog Devices Inc, ADV7301AKST Datasheet - Page 25

• Manufacturer Part Number: ADV7301AKST
• Description: IC DAC VIDEO HDTV 6-12BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7301AKST

• Rohs Status: RoHS non-compliant
• Applications: DVD, Set-Top Boxes
• Voltage - Supply, Analog: 2.37 V ~ 2.63 V
• Voltage - Supply, Digital: 2.37 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

REV. A
Subaddress
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
Register
SD Timing Register 0
SD Timing Register 1
SD F
SD F
SD F
SD F
SD F
SD Closed Captioning Extended Data on Even
SD Closed Captioning Extended Data on Even
SD Closed Captioning Data on Odd Fields
SD Closed Captioning Data on Odd Fields
SD Pedestal Register 0 Pedestal on Odd Fields
SD Pedestal Register 1 Pedestal on Odd Fields
SD Pedestal Register 2 Pedestal on Even Fields
SD Pedestal Register 3 Pedestal on Even Fields
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
Bit Description
SD Slave/Master Mode
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Min. Luma Value
SD Timing Reset
SD HSYNC Width
SD HSYNC to VSYNC
Delay
SD HSYNC to VSYNC
Rising Edge Delay (Mode 1
Only); VSYNC Width
(Mode 2 Only)
HSYNC to Pixel Data
Adjust
Fields
Fields
Table VIII. SD Registers
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
X
0
0
1
1
X
X
X
X
X
X
X
X
X
17
25
17
25
–25–
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
16
24
16
24
0
0
1
1
0
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
15
23
15
23
0
1
0
1
0
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
14
22
14
22
0
1
0
0
0
1
1
X
X
X
X
X
X
X
X
X
13
21
13
21
0
0
1
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
12
20
12
20
0
1
0
1
0
0
0
1
1
X
X
X
X
X
X
X
X
X
11
19
11
19
0
1
0
0
1
0
1
X
X
X
X
X
X
X
X
X
10
18
10
18
ADV7300A/ADV7301A
Slave Mode
Master Mode
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No Delay
2 Clock Cycles
4 Clock Cycles
6 Clock Cycles
–40 IRE
–7.5 IRE
A low-high-low
transistion will reset the
internal SD timing
counters.
Ta = 1 Clock Cycle
Ta = 4 Clock Cycles
Ta = 16 Clock Cycles
Ta = 128 Clock Cycles
Tb = 0 Clock Cycle
Tb = 4 Clock Cycles
Tb = 8 Clock Cycles
Tb = 18 Clock Cycles
Tc = Tb
Tc = Tb + 32 µs
1 Clock Cycle
4 Clock Cycles
16 Clock Cycles
128 Clock Cycles
0 Clock Cycle
1 Clock Cycle
2 Clock Cycles
3 Clock Cycles
Subcarrier Frequency
Bits 7–0
Subcarrier Frequency
Bits 15–8
Subcarrier Frequency
Bits 23–16
Subcarrier Frequency
Bits 31–24
Subcarrier Phase Bits
9–2
Extended Data Bits 7–0 00h
Extended Data Bits
15–8
Data Bits 7–0
Data Bits 15–8
Setting any of these bits
to 1 will disable
pedestal on the line
number indicated by
the bit settings.
Reset
08h
00h
16h
7Ch
F0h
21h
00h
00h
00h
00h
00h
00h
00h
00h