Z8622912SSC Zilog, Z8622912SSC Datasheet - Page 30

• Manufacturer Part Number: Z8622912SSC
• Description: IC CCD W/2ND I2C ADD 18-SOIC
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912SSC

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: No RoHS Version Available

INTERNAL REGISTERS
Information controlling the setup and operation of the
Z86229 are maintained in several registers. The user may
read or alter the contents of these registers as required.
Serial Status (SS) Register Address = Not Required
D
circuits are locked. This bit may be used as an indication
of the presence of a video signal.
D
Field 2, High = Field 1.
D
in the output buffer has not been read out and, new data has
been written over it.
D
than DAV is pending.
D
run has occurred.
D
Low = 1 byte, High = 2 bytes.
D
be read out.
D
is empty. Only the NOP, RESET, and READ instructions
may be sent if RDY is Low.
Configuration Register Address = 00h
D
lects PAL and Low selects NTSC. The default is NTSC.
Bit
Bit
0
1
2
3
4
5
6
7
0
–LOCK.
–FLD.
–ROVR.
–INTR.
–WOVR.
–RD2.
–DAV.
–RDY.
–TVS.
Figure 19. Configuration Register (Address = 00h)
RDY
R
D
res
D
7
7
This bit signals the current video field. Low =
This bit selects the television standard. High se-
Signals the number of bytes available for output.
Active High, indicating that data is available to
Active High, indicating that the port input buffer
Active High, indicating that an interrupt other
Active High, indicating that the internal sync
DAV
Active High, indicating that the data available
D
Figure 18. Serial Status Register
Active High, indicating a serial input data over-
R
D
res
6
6
(Address not required)
RD2
D
R
res
D
5
5
WOVR
D
D
res
R
4
4
INTR
R/W
VLK
D
R
D
3
3
ROVR FLD LOCK
R/W
D
HLK
R
D
2
2
MONO
D
R/W
R
D
1
1
R/W
TVS
D
R
D
0
0
When PAL is selected, the display defaults to 15 TV scan
lines per display row.
D
High indicates that the character luminance is output on all
three color pins (RGB). The default is Low, selecting COL-
OR operation.
D
used to lock the VCO (Low = Internal, High = HIN). The
default is Internal.
D
to establish a vertical sync lock (Low = Internal, High =
V
abled, the V
mode. Interrupts should not be selected in the Interrupt
Mask register if the VLK mode is used.
D
Display Register Address = 01h
D
mode (High = DROP SHADOW and Low = BOX). The de-
fault is Low.
D
acter row in a Text display (High = 15 lines/row and Low
= 13 lines/row). The default is Low.
D
display (High = Disabled, Low = Enabled). The default is
Low.
D
CAPTION mode (High = DROP SHADOW and Low =
BOX). The default is Low.
D
acter row in a CAPTION display (High = 15 lines/row and
Low = 13 lines/row). The default is Low.
D
TION display (High = Disabled, Low = Enabled). The de-
fault is Low.
Bit
1
2
3
4
0
1
2
3
4
5
IN
–MONO.
–HLK.
–VLK.
–D
–TDRP.
–T15.
–TENH.
–CDRP.
–C15.
–CENH.
). The default is Internal. When the Internal lock is en-
R/W
7
O15 ODRP CENH
D
.
Figure 20. Display Register (Address = 01h)
7
Reserved.
This bit selects the number of TV lines per char-
This bit selects the number of TV lines per char-
This bit selects the horizontal signal source to be
This bit selects the vertical signal source to be used
This bit selects Drop Shadow or Full Box in Text
This bit enables Enhanced Attributes for a Text
This bit selects Drop Shadow or Full Box in
This bit enables Enhanced Attributes for a CAP-
This bit selects monochrome operation. Active
R/W
IN
D
/INTRO pin defaults to the INTRO output
6
R/W
D
5
C15
R/W
D
4
CDRP TENH
R/W
D
3
R/W
D
2
R/W
T15
D
1
ZiLOG
TDRP
R/W
D
0