PCA9555PW,112 NXP Semiconductors, PCA9555PW,112 Datasheet - Page 14

• Manufacturer Part Number: PCA9555PW,112
• Description: IC I/O EXPANDER I2C 16B 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9555PW,112

• Package / Case: 24-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA
• Number Of Lines (input / Output): 16 / 16
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 2.3 V to 5.5 V
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16
• Number Of Output Lines: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3986-5; 935269569112; PCA9555PW; PCA9555PW

NXP Semiconductors
7. Characteristics of the I
PCA9555_8
Product data sheet
6.5.3 Interrupt output
7.1.1 START and STOP conditions
7.1 Bit transfer
The open-drain interrupt output is activated when one of the port pins changes state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read (see
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 15. Bit transfer
Fig 16. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 08 — 22 October 2009
16).
data valid
data line
stable;
16-bit I
Figure
2
allowed
change
of data
C-bus and SMBus I/O port with interrupt
15).
Figure
13). A pin configured as an
STOP condition
mba607
P
PCA9555
© NXP B.V. 2009. All rights reserved.
mba608
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