PCA9673DB,118 NXP Semiconductors, PCA9673DB,118 Datasheet - Page 21

• Manufacturer Part Number: PCA9673DB,118
• Description: IC I/O EXPANDER I2C 16B 24SSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9673DB,118

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283556118; PCA9673DB-T; PCA9673DB-T

NXP Semiconductors
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PCA9673_1
Product data sheet
Fig 26. I
Fig 27. Reset timing
t
t
C
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
Rise and fall times refer to V
2
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
C-bus timing diagram
P0n, P1n
RESET
SCL
SDA
protocol
SDA
f
SCL
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
50 %
t
t
SU;STA
rec(rst)
t
BUF
condition
START
(S)
t
START
HD;STA
IL
30 %
f
.
and V
t
LOW
t
r
IH
.
MSB
bit 7
(A7)
Remote 16-bit I/O expander for Fm+ I
t
HIGH
Rev. 01 — 1 February 2007
t
SU;DAT
t
f
1
/f
bit 6
(A6)
SCL
t
HD;DAT
(R/W)
bit 0
t
VD;DAT
acknowledge
t
w(rst)
50 %
(A)
ACK or read cycle
t
VD;ACK
t
2
t
rst
rst
C-bus with interrupt and reset
50 %
condition
STOP
(P)
50 %
IL
t
SU;STO
of the SCL signal) in order to
002aab175
output off
PCA9673
© NXP B.V. 2007. All rights reserved.
002aac282
f
is specified at
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