SI2401-FS Silicon Laboratories Inc, SI2401-FS Datasheet - Page 18

• Manufacturer Part Number: SI2401-FS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Integrated Global DAAr

Specifications of SI2401-FS

• Package / Case: 16-SOIC (3.9mm Width)
• Data Format: V.21, V.22, V.23, Bell 103, Bell 212A
• Baud Rates: 2.4k
• Interface: UART
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Package: 16SOIC
• Main Category: Chipset
• Sub-category: ISOmodem
• Maximum Data Rate: 2.4 Kbps
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Digital
• Typical Supply Current: 10 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1167 - BOARD EVAL SI2401 UART INTERFACE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1095

Si2401/Si3008
To summarize, when receiving HDLC frames, the host
begins receiving data asynchronously from the Si2401.
When each byte is received, the host should check the
EOFR pin (or the ninth bit). If the EOFR pin (or the ninth
bit) is low, the data is valid frame data. If the EOFR pin
(or the ninth bit) is high, the data is a frame result word.
4.8. Fast Connect
In modem applications that require fast connection
times, it is possible to reduce the length of the
handshake.
Additional modem handshaking control can be adjusted
through the registers shown in Table 11. These registers
are most useful if the user has control of both the
originating and answering modems.
When the fast connect settings are used, there may be
unintended data received initially.The host must tolerate
these bytes.
18
(or bit 9)
EOFR
RXD
CTS
TXD
Si2401 ready for byte 1 of frame N
Start
Host begins frame N
Note: Figure not to scale.
Receive Data
Start
Stop
(CTS used as normal flow control.)
Start
Frame N
CRC Byte 1
Figure 4. HDLC Timing
A. Frame Transmit
B. Frame Receive
Rev. 1.1
Stop
4.9. Clock Generation Subsystem
The Si2401 contains an on-chip clock generator. Using
a single master clock input, the Si2401 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 27 MHz or
4.9152 MHz clock on XTALI or a 4.9152 MHz crystal
across XTALI and XTALO form the master clock for the
Si2401. This clock source is sent to an internal phase-
locked loop (PLL) that generates all necessary internal
system clocks. The PLL has a settling time of ~1 ms.
Data on RXD should not be sent to the device prior to
settling of the PLL. By default, the Si2401 assumes a
4.9152 MHz clock input. If a 27 MHz clock on XTALI is
used, a pulldown resistor <10 kΩ must be placed
between GPIO4 (Si2401, pin 11) and GND.
Start
Host finished sending frame N
Stop
Si2401 detects end of frame N.
CRC Byte 2
Si2401 ready for byte 1
of frame N + 1.
Stop
Host begins frame N + 1
Start
Start
Frame Result Word
Frame N + 1
Stop