AMIS49587C5871G ON Semiconductor, AMIS49587C5871G Datasheet - Page 22

• Manufacturer Part Number: AMIS49587C5871G
• Description: IC MODEM PLC 50/60MHZ 28PLCC
• Manufacturer: ON Semiconductor

Specifications of AMIS49587C5871G

• Baud Rates: Selectable
• Interface: SCI
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -

6.2
MODULATOR)
direct digital synthesis (DDS) of the sine wave signals is
performed under the control of the microprocessor. After a
signal conditioning step, a digital to analog conversion is
performed. As for the receive path, a sigma delta
6.2.1 ARM Interface and Control
registers R_TX_DATA, 2 control registers R_TX_CTRL
and R_ALC_CTRL, a flag TX_RXB defining transmit and
receive and 2 16- -bit wide frequency step registers R_FM
and R_FS defining f
(space frequency = data 0). All these registers are memory
mapped. Some of them are for internal use only and cannot
be accessed by the user.
address, CRC) is done by the ARM.
6.2.2 Sine Wave Generator
DDS. The synthesizer generates in transmission mode a sine
wave either for the space frequency (f
mark frequency (f
generates the sine and cosine waves for the mixing process,
f
quadrature). The space and mark frequencies are defined in
an individual step 16 bit wide register.
SI
For the generation of the space and mark frequencies, the
The interface with the ARM consists in a 8- -bit data
The processing of the physical frame (preamble, MAC
A sine wave is generated with a direct digital synthesizer
, f
TRANSMITTER PATH DESCRIPTION (S- -FSK
SQ
, f
MI
TX_EN
ALC_IN
TX_OUT
, f
MQ
M
(space and mark signals in phase and
, data1). In reception the synthesizer
M
(mark frequency = data 1) and f
Transmitter (S--FSK Modulator)
S
, data 0) or for the
control
Figure 17. Transmitter Block Diagram
Filter
ALC
LP
http://onsemi.com
D/A
S
22
modulation technique is used. In the analog domain, the
signal is low pass filtered, in order to remove the high
frequency quantization noise, and passed to the automatic
level controller (ACL) block, where the level of the
transmitted signal can be adjusted. The determination of the
signal level is done through the sense circuitry.
The space and mark frequency can be calculated as:
•
•
Or the content of both R_FS[15:0] and R_FM[15:0] are
defined as:
•
•
(when TX_RXB goes from 0 to 1) the phase accumulator
Table 24. FS AND FM STEP REGISTERS
R_FM[15:0]
After a hard or soft reset or at the start of the transmission
R_FS[15:0]
f
f
R_FS[15:0]_dec = Round(2
R_FM[15:0]_dec = Round(2
Where f
clock frequency.
Register
S
M
& Sine Synthesizer
= R_FS[15:0]_dec x f
ARM
= R_FM[15:0]_dec x f
Transmit Data
f
MI
TO RECEIVER
DDS
f
MQ
= 3 MHz is the direct digital synthesizer
f
SI
Reset
0000h
0000h
Hard
f
SQ
DDS
DDS
0000h
0000h
Reset
Soft
Interface
18
/2
Control
18
ARM
/2
18
x f
x f
&
18
S
M
/f
Step register for the
space frequency f
Step register for the
mark frequency f
/f
DDS
DDS
Description
)
)
M
S