QT60248-ASG Atmel, QT60248-ASG Datasheet - Page 10

• Manufacturer Part Number: QT60248-ASG
• Description: IC SENSOR QMATRIX 24CHAN 32TQFP
• Manufacturer: Atmel
• Series: QMatrix™, QProx™r
• Type: Capacitiver

Specifications of QT60248-ASG

• Number Of Inputs/keys: 24 Key
• Resolution (bits): 9, 11 b
• Data Interface: Serial, SPI™
• Voltage - Supply: 3 V ~ 5 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Output Type: Logic
• Interface: SPI
• Input Type: Logic
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• For Use With: 427-1087 - BOARD EVAL QT60248-AS QMATRIX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 427-1108

3 Serial Communications
These devices use SPI communications, in slave mode.
The host device always initiates communications sequences;
the QT is incapable of chattering data back to the host. This is
intentional for FMEA purposes so that the host always has total
control over the communications with the QT60xx8. In SPI
mode the device is a slave, so that even return data following a
command is controlled by the host.
A command from the host always ends in a response of some
kind from the QT. Some transmission types from the host or the
QT employ a CRC check byte to provide for robust
communications.
A DRDY line is provided that handshakes transmissions.
Generally this is needed by the host from the QT to ensure that
transmissions are not sent when the QT is busy or has not yet
processed a prior command.
Initiating or Resetting Communications: After a reset, or,
should communications be lost due to noise or out-of-sequence
reception, the host should send a 0x0f (return last command)
command repeatedly until the compliment of 0x0f, i.e. 0xf0, is
received back. Then, the host can resume normal run mode
communications from a clean start.
Poll rate: The typical poll rate in normal ‘run’ operation should
be no faster than once per 10ms; 25ms is more than fast
enough to extract status data using the 0x06 command (report
first key: see page 13) in most situations. Streaming multi-byte
response commands like the 0x0d command (dump setups: see
page 13) or multi-byte response commands like 0x07 can and
should pace at the maximum possible rate.
Run Poll Sequence: In normal run mode the host should limit
traffic with a minimalist control structure (see also Section 4.18).
The host should just send a 0x06 command until something
requires a deeper state inspection. If there is more than one key
in detect, the host should use 0x07 to find which additional keys
are in detect. If there is an error, the host should ascertain the
error type based on commands 0x0b and 0x0c and take
appropriate action. Issuing a 0x07 command all the time is
wasteful of bandwidth, requires more host processor time, and
actually conveys less information (no error flags are sent via a
0x07 command).
3.1 DRDY Pin
DRDY is an open-drain output with an internal 20K ~ 50K pullup
resistor.
Serial communications pacing is controlled by this pin. The host
is permitted to send data only when DRDY is high. After a byte
is received DRDY will always go low even if only for a few
microseconds; during this period the host should not send data.
Therefore, after each byte transmission the host should first
check that DRDY is high again.
If the host desires to send a byte to the QT it should behave as
follows:
lQ
1. If DRDY is low, wait
2. If DRDY is high: send a command to QT
3. Wait at least 40µs (time S5 in Figure 3-3: DRDY is
4. Wait until DRDY is high (it may already be high again)
5. Send next command or a null byte 0x00 to QT
guaranteed to go low before this 40µs expires)
10
The time it takes for DRDY to go high again after a command
depends on the command. Following is a list of commands and
the time required to process them and then raise DRDY:
Other DRDY specs:
3.2 SPI Communications
SPI communications operates in slave mode only, and obeys
DRDY control signaling. The clocking is as follows:
SPI mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for
MISO - Master in / Slave out data pin; used as an output for
Host MCU
0x0E Eeprom CRC
0x01 Load Setups
All other commands:
Min time DRDY is low: 1µs
Min time DRDY is low
P_OUT1
P_OUT2
SPI Clock Rate
data from the host (master). This pin should be connected
to the MOSI (DO) pin of the host device.
data to the host. This pin should be connected to the MISO
after reset:
MISO
MOSI
P_IN
SCK
1.5MHz
400kHz
100kHz
Clock idle:
Clock shift out edge:
Clock data in edge:
Max clock rate:
50kHz
Host MCU
P_OUT
Figure 3-2 Filtered SPI Connections
Figure 3-1 Basic SPI Connections
MISO
MOSI
P_IN
SCK
Recommended Values of Ra & Ca
Ca
Ca
Ra
Ra
Ra
Ra
Ra
1K
[ 25ms
[ 25ms
[ 2ms between bytes;
[ 40µs after CRC byte is sent
1ms
1,000
2,200
2,200
1nF
Ca
Ca
Ca
680
Ra
QT60248-AS R4.02/0405
Falling
High
Rising
1.5MHz
DRDY
SS
SCK
MISO
MOSI
RESET
QT60xx8 Circuit
QT60xx8
X drives
DRDY
SS
SCK
MISO
MOSI
Y Lines
shown)
shown)
(1 of 8
(1 of 3
100pF
270pF
470pF
1nF
Ca
1K
1K
Xn
Yn