MAX9209EUM+D Maxim Integrated Products, MAX9209EUM+D Datasheet - Page 12

• Manufacturer Part Number: MAX9209EUM+D
• Description: IC SERIALIZER PROG 48-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9209EUM+D

• Function: Serializer
• Data Rate: 1.785Gbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVDS
• Number Of Inputs: 21
• Number Of Outputs: 3
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
Programmable DC-Balanced
21-Bit Serializers
12
______________________________________________________________________________________
PWRDWN
TxCLK IN
TxIN
CYCLE N - 1
TxIN15
TxCLK OUT+
TxCLK OUT-
TxOUT2
TxOUT1
TxOUT0
TxIN8
TxIN1
7
7
7
TxIN14
TxIN7
TxIN0
TxIN20
TxIN13
TxIN6
PLL
7:1
7:1
7:1
21:3 SERIALIZER
TxIN19
TxIN12
MAX9209
MAX9213
TxIN5
AC-Coupling Benefits
TxIN18
TxIN11
TxIN4
CYCLE N
TxIN17
TxIN10
TxIN3
R
R
R
R
O
O
O
O
TxIN16
TxIN9
TxIN2
TxOUT
TxCLK OUT
TxIN15
TxIN8
TxIN1
TRANSMISSION LINE
TxIN14
TxIN7
TxIN0
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately ±1V common-
mode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
100Ω
100Ω
100Ω
100Ω
R
R
R
R
TxIN20
TxIN13
RxCLK IN
TxIN6
T
T
T
T
=
=
=
=
RxIN
TxIN19
TxIN12
TxIN5
TxIN18
TxIN11
TxIN4
3:21 DESERIALIZER
CYCLE N + 1
MAX9210
MAX9214
TxIN17
TxIN10
TxIN3
TxIN16
TxIN9
TxIN2
PLL
1:7
1:7
1:7
TxIN15
TxIN8
TxIN1
7
7
TxIN14
7
TxIN7
TxIN0
RxOUT
PWRDWN
RxCLK OUT