DS92LV1212TMSA National Semiconductor, DS92LV1212TMSA Datasheet - Page 12

• Manufacturer Part Number: DS92LV1212TMSA
• Description: IC DESERIALZR RANDOM LOCK 28SSOP
• Manufacturer: National Semiconductor

Specifications of DS92LV1212TMSA

• Function: Deserializer
• Data Rate: 400Mbps
• Input Type: LVDS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 10
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV1212TMSA

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Deserializer Pin Description
RCLK_R/F
RI+
RI−
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
SYNC PTRN
DATA (0–9)
DATA (0–9)
DATA (0–9)
DATA (0–9)
* Inverted
**If the Rx is locked when REN goes low the LOCK* output will go Tri-state on the rising edge of REFCLK. If the Rx is not locked when REN goes low the LOCK*
output will remain active. It will be high as the Rx is not locked but should the Rx attain lock the LOCK* output will go low to indicate lock.
Truth Table
RI
X
Z
Pin Name
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
DATA (0–9)*
DATA (0–9)*
RI−
X
Z
I/O
O
O
I
I
I
I
I
I
I
I
I
I
RCLK_R/F
X
X
X
X
X
1
0
14, 20, 22
(Continued)
1, 12, 13
21, 23
4, 11
No.
10
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
2
5
6
7
9
8
3
REFCLK
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
12
REN
X
X
0
0
1
1
1
PWRDN
X
0
1
1
1
1
1
Description
RCLK
CLK
L
K
Z
Z
Z
Z
H
L
LOCK
PLL **
Z
Z
1
0
0
Z **
SYNC PTRN
ROUT (0–9)
DATA
DATA
Z
Z
Z
Z