FIN12ACMLX Fairchild Semiconductor, FIN12ACMLX Datasheet - Page 14

• Manufacturer Part Number: FIN12ACMLX
• Description: IC SERIALIZER/DESERIALIZER 32MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN12ACMLX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN12ACMLX; FIN12ACMLXTR

FIN12AC Rev. 1.1.2
© 2006 Fairchild Semiconductor Corporation
Notes
3 Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
4 The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
5 Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
6 Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
Control Logic Timing Controls
Note:
7 Serializer enable time includes the amount of time required for internal voltage and current references to stabilize.
Capacitance
t
t
t
t
t
t
Symbol
t
Symbol
t
PLZ
PZL
PLZ
PZL
PLZ
PZL
C
PHL_DIR
PLH_DIR
IO-DIFF
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
occurs approximately 8 bit times after a data transition or 6 bit times after the falling edge of CKSO. Variation of the
data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path and
propagation delay differences on the various data pins. Note that if the CKREF is not equal to STROBE for the
serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13 bit times.
This time is significantly less than the PLL lock time and does not limit overall system startup time.
C
C
, t
, t
, t
, t
, t
, t
IN
IO
:
PHZ
PZH
PHZ
PZH
PHZ
PZH
,
Propagation Delay
DIRI-to-DIRO
Propagation Delay
DIRI-to-DP
Propagation Delay
DIRI-to-DP
Deserializer Disable Time
S0 or S1 to DP
Deserializer Enable Time
S0 or S1 to DP
Serializer Disable Time
S0 or S1 to CKSO, DS
Serializer Enable Time
S0 or S1 to CKSO, DS
Capacitance of Input Only Signals, CKREF,
STROBE, S1, S2, DIRI
Capacitance of Parallel Port Pins DP[1:12]
Capacitance of Differential I/O Signals
Parameter
(7)
Parameter
DIRI LOW-to-HIGH or HIGH-to-LOW
DIRI LOW-to-HIGH
DIRI HIGH-to-LOW
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
DIRI = 0, S1(2) = 0 and S2(1) = LOW-to-HIGH
Figure 21
DIRI = 1, S1(2) = 0 and S2(1) = HIGH-to-LOW
Figure 20
DIRI = 1, S1(2) and S2(1) = LOW-to-HIGH
Figure 20
Test Conditions
14
DIRI = 1, S1 = 0, S2=0,
V
DIRI = 1, S1 = 0, S2=0,
V
DIRI = 1, S2=0, S1 = 0,
V
DD
DD
DD
= 2.5V
= 2.5V
= 2.5V
Test Conditions
Min. Typ. Max. Units
Min. Typ. Max. Units
2
2
2
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17
25
25
25
25
65
2
pF
pF
pF
ns
ns
ns
ns
µs
ns
ns