DS2176Q Maxim Integrated Products, DS2176Q Datasheet - Page 3

• Manufacturer Part Number: DS2176Q
• Description: IC BUFFER RECEIVE T1 28-PLCC
• Manufacturer: Maxim Integrated Products
• Type: Bufferr

Specifications of DS2176Q

• Tx/rx Type: T1
• Delay Time: 100ns
• Capacitance - Input: 5pF
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-LCC, 28-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
SYMBOL
RMSYNC
RCLK
RSER
A
B
C
D
SCHCLK
SM0
SM1
V
S/
FMS
SFSYNC
SIGFRZ
SMSYNC
SBIT8
SSER
SYSCLK
SCLKSEL
V
SIGN
SLIP
ALN
SS
DD
P
TYPE
O
O
O
O
O
O
O
–
–
I
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
Signaling Inhibit. When low, ABCD signaling updates are disabled for
a period determined by SM0 and SM1, or until returned high.
Receive Multifram Sync. Must be pulsed high at multiframe
boundaries to establish frame and multiframe alignment.
Receive Clock. Primary 1.544 MHz clock.
Receive Serial Data. Sampled on Falling edge of RCLK.
Robbed-Bit Signaling Outputs.
System Channel Clock. Transitions high on channel boundaries; useful
for serial to parallel conversion of channel data.
Signaling Modes 0 and 1. Select signaling supervision technique.
Signal Ground. 0.0 volts.
Serial/Parallel Select. Tie to V
V
Frame Mode Select. Tie to V
193E (extended).
Align. Recenters buffer on next system side frame boundary when
forced low.
System Frame Sync. Rising edge establishes start of frame.
Signaling Freeze. When high, indicates signaling updates have been
disabled internally via a slip or externally by forcing
System Multiframe Sync. Slip-compensated multiframe output;
indicates when signaling updates are made.
System Bit 8. High during the LSB time of each channel. Used to
reinsert extracted signaling into outgoing data stream.
Frame Slip. Active low, open collector output. Held low for 65
SYSCLK cycles when a slip occurs.
System Serial Out. Updated on rising edge of SYSCLK.
System Clock. 1.544 or 2.048 MHz data clock.
System Clock Select. Tie to V
2.048 MHz.
Positive Supply. 5.0 volts.
PIN DESCRIPTION Table 1
DD
for serial.
3 of 15
SS
SS
SS
to select 193S(D4) framing to V
for 1.544 MHz applications, to V
for parallel backplane applications, to
SIGH
low.
DD
DS2176
DD
for
for