HBLXT9863AHC.B4 Intel, HBLXT9863AHC.B4 Datasheet
HBLXT9863AHC.B4
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HBLXT9863AHC.B4 Summary of contents
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... Advanced 10/100 Unmanaged Repeater The LXT9883 is an advanced, 3.3V, 8-port 10/100 repeater. The LXT9883 is compatible with previous generations of Intel repeaters from the LXT980 and LXT918 families. Eight ports directly support 100BASE-TX/10BASE-T copper media. Two additional Media Independent Interface (MII) ports (10/100Mbps selectable) connect to Media Access Controllers (MACs) for bridge/switch applications. The LXT9863 offers the same features and functionality in a six-port device. This data sheet uses the singular designation “ ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1.0 Block Diagram ............................................................................................................................... 7 2.0 Pin Assignments and Signal Descriptions ................................................................................. 8 3.0 Functional Description................................................................................................................ 16 3.1 Introduction ......................................................................................................................... 16 3.2 Port Configuration............................................................................................................... 17 3.2.1 Auto-Negotiation .................................................................................................... 17 3.2.2 Link Establishment and Port Connection ............................................................... 18 3.3 Interface ...
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Contents 4.2.3 Power and Ground Plane Layout Considerations.................................................. 33 4.2.4 Chassis Ground ..................................................................................................... 34 4.2.5 The RBIAS Pin....................................................................................................... 34 4.2.6 MII Terminations .................................................................................................... 35 4.2.7 Twisted-Pair Interface............................................................................................ 36 4.2.7.1 Magnetics Information............................................................................ 36 4.2.8 Clock...................................................................................................................... 37 4.2.9 LED Circuits........................................................................................................... 39 4.2.9.1 ...
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Tables 1 MII #1 Signal Descriptions ............................................................................................................ 9 2 MII #2 Signal Descriptions .......................................................................................................... 10 3 Inter-Repeater Backplane Signal Descriptions ........................................................................... 11 4 Twisted-Pair Port Signal Descriptions ........................................................................................ 13 5 LED Signal Descriptions ............................................................................................................. 14 6 Power Supply and Indication ...
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Contents Revision History Date Revision August 2001 003 February 2001 002 6 Page Description 44 Modify the Absolute Maximum Ratings Supply Voltage value to 4.0V. 21, 37 Modified clock requirements language. 21 Replaced TBD value under reset to 3.15V. Replaced ...
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Block Diagram Figure 1. LXT98x3 Block Diagram 10 Mbps 10M IRB Backplane 100 Mbps 100M IRB Backplane Port & Mgmt Serial LED Status Indicators Drivers Datasheet Document #: 249115 Revision #: 003 Rev. Date: 08/07/01 Advanced 10/100 Unmanaged Repeater ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 2.0 Pin Assignments and Signal Descriptions Figure 2. LXT9883 Pin Assignments RESET....... 53 CLK25....... 54 N/C....... 55 N/C....... 56 N/C....... 57 N/C....... 58 N/C....... 59 N/C....... 60 VCC....... 61 GND....... 62 N/C....... 63 N/C....... ...
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Table 1. MII #1 Signal Descriptions 1, 2 Pin Symbol Type I MII1_SPD MII1_RXD0 32 MII1_RXD1 O MII1_RXD2 34 MII1_RXD3 MII1_RXDV O 29 MII1_RXCLK O 26 MII1_RXER MII1_TXER MII1_TXCLK O I ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 2. MII #2 Signal Descriptions 1, 2 Pin Symbol Type I 18 MII2_SPD PU 205 MII2_RXD0 206 MII2_RXD1 O 207 MII2_RXD2 208 MII2_RXD3 O 204 MII2_RXDV O 203 MII2_RXCLK O 202 MII2_RXER MII2_TXER ...
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Table 3. Inter-Repeater Backplane Signal Descriptions 1, 2 Pin Symbol Type 39 COMP_SEL AI A I/O 3 IR100CFS I/O 37 IR100CFSBP OD I/O 38 IR100SNGL Schmitt PU I/O 40 IR100COL Schmitt IR100DEN I/O ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 3. Inter-Repeater Backplane Signal Descriptions (Continued Pin Symbol Type I/O 11 IR10DAT OD PD I/O Tri-state 12 IR10CLK Schmitt IR10DEN I IR10ENA PU I/O OD ...
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Table 4. Twisted-Pair Port Signal Descriptions Pin Symbol Type 107, 108 TPOP1, TPON1 111, 110 TPOP2, TPON2 121, 122 TPOP3, TPON3 125, 124 TPOP4, TPON4 Caution: AO 136, 137 TPOP5, TPON5 140, 139 TPOP6, TPON6 150, 151 TPOP7, TPON7 154, ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 5. LED Signal Descriptions Pin Symbol Type 184 LEDSEL0 O - OD/OS 185 LEDSEL1 175 LEDABGSEL O - OD/OS 183 AUTOBLINK O - OD/OS 83 LEDDAT 84 LEDLAT 82 LEDCLK 176 PORT8_LED1 171 ...
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Table 5. LED Signal Descriptions (Continued) Pin Symbol Type 186 COL100_LED O - OD/OS 183 ACT10_LED O - OD/OS 184 ACT100_LED O - OD/ Input Output, I/O = Input/Output Digital Analog, ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 6. Power Supply and Indication Signal Descriptions (Continued) Pin Symbol Type 102 RBIAS RPS_PRES RPS_FAULT Input Output, I/O = Input/Output, D ...
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This multi-port repeater provides six (LXT9863) or eight (LXT9883) 10BASE-T/100BASE-TX ports. In addition, each device also provides two Media Independent Interface (MII) expansion ports that may be connected to 10/100 MACs. The LXT98x3 provides two repeater state machines and two ...
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... Each 10BASE-T port can detect and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T interface provides integrated filters using Intel’s patented filter technology. These filters facilitate low-cost stack designs to meet EMI requirements. ...
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Figure 4. MII Interface MAC 3.4 Repeater Operation The LXT98x3 contains two internal repeater state machines — one operating at 10 Mbps and the other at 100 Mbps. The LXT98x3 automatically switches each port to the correct repeater, once the ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater • Un-partition. The un-partition algorithm, which complies with IEEE specification 802.3aa, un- partitions a port on either transmit or receive of at least 450-560 bits without collision. • Isolate. The LXT98x3 isolates any port ...
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Each supply input should be decoupled to ground. Refer to ground pin assignments, and to the 3.5.2 Clock A stable, external 25MHz reference clock source (TTL) is required to the CLK25 pin. The reference clock is used to generate transmit ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 3.6.2 LED Event Stretching Short lived LED status events are stretched so they may be observed by the human eye. Refer to the LED1 Modes section for stretching specifics. 3.6.3 Serial LED ...
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Serial LED Signals The LED serial interface bus consists of three LXT98x3 outputs: clock (LEDCLK), parallel load clock (LEDLAT), and output data (LEDDAT). Refer to and to Figure 14 on page 40 and Table 8 for details on the ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater There are two display modes for the activity bar graphs, Base-2 and Base-10. The modes are selected via the LEDABGSEL pin. Refer to lit when the percent activity value associated with that step is ...
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LED Mode 1 Mode 1 operations are described in Table 11. LED Mode 1 Indications LED Operating Mode 10 Mbps operation PORTnLED1 100 Mbps operation 10 Mbps operation PORTnLED2 100 Mbps operation AUTOBLINK active PORTnLED3 AUTOBLINK inactive Collision and ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 12. LED Mode 2 Indications Operating LED Mode PORTnLED1 Any PORTnLED2 AUTOBLINK active PORTnLED3 AUTOBLINK inactive Collision and Any Activity LEDs RPS Fault Any Global Fault Any 1. Refer to Table 10: LED ...
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Table 13. LED Mode 3 Indications LED Operating Mode 10 Mbps operation PORTnLED1 100 Mbps operation PORTnLED2 Any AUTOBLINK active PORTnLED3 AUTOBLINK inactive Collision and Any Activity LEDs Global Fault Any RPS Fault Any 1. Refer to Table 10: LED ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 3.6.6.4 LED Mode 4 Mode 4 operations are described in Table 14. LED Mode 4 Indications LED Operating Mode 10 Mbps operation PORTnLED1 100 Mbps operation 10 Mbps operation PORTnLED2 100 Mbps operation AUTOBLINK ...
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Operation 3.7.2.1 MAC IRB Access The MACACTIVE pin allows an external MAC or other digital ASIC to interface directly to the 10 Mbps IRB. When the MACACTIVE pin is asserted, the LXT98x3 drives the IR10CFS and IR10CFSBP signals ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 8. IRB Block Diagram Hub Board 1 ’245 Hub Board 2 ’245 Hub Board n ’245 This diagram shows a single IRB. The LXT98x3 actually has two independent IRBs, one per speed/segment. Digital ...
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Table 16. IRB Signal Details Name Pad Type IR100DAT<4:0> Digital IR100CLK Digital IR100DV Digital, Open Drain IR100CFS Analog IR100CFSBP Analog IR100COL Digital IR100SNGL Digital IR100DEN Digital, Open Drain IR10DAT Digital, Open Drain IR10CLK Digital IR10ENA Digital, Open Drain IR10CFS Analog ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 9. LXT9883 MII Operation The two LXT9883 MII ports act as the PHY side of the MII. An external MAC sends TX Data to the LXT9883 to be repeated to the network. The ...
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... DC-to-DC converters. Many of these issues can be improved by following good general design guidelines. In addition, Intel recommends filtering between the power supply and the analog VCC pins of the LXT98x3. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT98x3, which helps line performance ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 4.2.4 Chassis Ground For ESD protection, create a separate chassis ground. For isolation, encircle the board and place a “moat” around the signal ground plane to separate signal ground from chassis ground. Chassis ground ...
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Figure 10. Power and Ground Connections LXT9883 VCCT GND VCC GND RBIAS GND VCC GND VCC GND 4.2.6 MII Terminations The LXT98x3 MIIs have high output impedance (250-350 ). To minimize reflections, serial termination resistors are recommended on all MII ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 4.2.7 Twisted-Pair Interface The LXT98x3 transmitter uses standard 1:1 magnetics for both receive and transmit. Nonetheless, system designers should take precautions to minimize parasitic shunt capacitance and meet return loss specifications. These steps include: ...
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Table 17. LXT98x3 Magnetics Specifications Parameter Return Loss - standard 4.2.8 Clock A stable, external 25MHz reference clock source (TTL) is required to the CLK25 pin. The reference clock is used to generate transmit signals and recover receive signals. A ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 11. Typical Twisted-Pair Port Interface and Power Supply Filtering 270 pF 5% LXT98x3 TPFIP TPIP TPIN 270 pF 5% TPOP .01 F TPON VCCT 0.1 F GND Figure 12. Typical Reset Circuit NOTE: ...
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LED Circuits 4.2.9.1 Direct Drive LEDs Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected, via a current limiting resistor positive voltage rail. The LEDs are turned on when the output pin drives ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 4.2.9.3 Serial LEDs The LXT98x3 provides a serial interface to support additional LED options. Standard shift registers, either 74X595s (8-bit Serial-to-Parallel with Output Registers) or 74X164s (8-bit S/P without registers) can be used to ...
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Inter-Repeater Backplane Compatibility The Inter-repeater Backplane (IRB) comprises two parts: • Local—the backplane between cascaded devices on the same board. • Stack—the backplane between multiple boards. Each of these backplanes consists of both analog and digital signals. 4.3.1 Local ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater • A LXT98x3-based board configured for 3.3V backplane operation and LXT98x or LXT91x based boards (5V only). • A LXT98x3-based board configured for 3.3V backplane operation and a LXT98x3-based board configured for 5V backplane ...
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Figure 16. Typical 100 Mbps IRB Implementation Stack or Segment Connector ’245 IR100CLKBP IR100CLK A B IR100DATBP IR100DAT IR100DVBP\ IR100DV\ IR100DEN\ DIR 91 ISOLATE ENA 1%* 1 IR100CFSBP\ COMP_SEL 1. In stacked configurations, all devices with FPS are ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 5.0 Test Specifications Note: Table 19 through Table 34 the LXT98x3 and are subject to change. Final values will be guaranteed by test except, where noted, by design. The minimum and maximum values listed ...
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Table 22. I/O Electrical Characteristics Parameter Sym Input Low voltage V IL Input High voltage V IH Hysteresis voltage – Output Low voltage V OL Output Low voltage (LED) V OLL Output High voltage V OH Input Low current I ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Table 23. 100 Mbps IRB Electrical Characteristics (Continued) Parameter 5.0V Operation single drive IR100CFS current collision single drive IR100CFSBP current collision single drive IR100CFS/BP voltage collision 1. Typical values are at 25° C and ...
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Table 25. 100BASE-TX Transceiver Electrical Characteristics Parameter Symbol Peak differential output voltage V (single ended) Signal amplitude symmetry Signal rise/fall time Trf Rise/fall time symmetry Trfs Duty cycle distortion Overshoot Vo 1. Typical values are at 25 °C and are ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 18. 100 Mbps TP Port-to-Port Delay Timing Normal Propagation TP Input Output Collision Jamming P Input #1 TP Input # Output Jam Table 27. 100 Mbps TP ...
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Figure 19. 100BASE-TX MII-to-TP Port Timing TX_CLK t 2A TXD, TX_EN, TX_ER t 2C CRS TPOP/N Table 28. 100BASE-TX MII-to-TP Port Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 20. 100BASE-TX TP-to-MII Timing TPIP CRS RXD, RX_DV, RX_ER RX_CLK t 3F COL Table 29. 100BASE-TX TP-to-MII Timing Parameters Parameter Sym t TPIP CRS asserted t TPIP/N quiet to ...
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Figure 21. 10BASE-T MII-to-TP Timing TX_CLK t 10A TXD, TX_EN, TX_ER t 10C CRS Table 30. 10BASE-T MII-to-TP Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 22. 10BASE-T TP-to-MII Port Timing TPIP/N t 11A CRS RXD, RX_DV, RX_ER RX_CLK t 11D COL Table 31. 10BASE-T TP-to-MII Port Timing Parameters Parameter Sym t TPIP CRS asserted 11A CRS ...
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Figure 23. 100 Mbps TP-to-IRB Timing TPIP/N t 12A IR100DV IR100CFS 1R100COL IR100DAT<4:0> IR100CLK Table 32. 100 Mbps TP-to-IRB Timing Parameters Parameter TPIP/N to IR100DV Low IR100DAT to IR100CLK setup time. IR100DAT to IR100CLK hold time. 1. This table contains ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater Figure 24. 10 Mbps TP-to-IRB Timing TPIP/N t 13A IR10ENA IR10DAT IR10CLK Table 33. 10 Mbps TP-to-IRB Timing Parameters 2 Parameter Symbol t TPIP/N to IR10ENA Low 13A IR10CLK rising edge to t 13B ...
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Figure 25. 10 Mbps IRB-to-TP Port Timing MACACTIVE t 14A IR10ENA IR10DAT IR10CLK TPOP/N Table 34. 10 Mbps IRB-to TP Port Timing Parameters Parameter Symbol MACACTIVE to IR10ENA t 14A 3 assertion delay IR10DAT (input) to IR10CLK t 14B setup ...
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LXT9883/9863 — Advanced 10/100 Unmanaged Repeater 6.0 Mechanical Specifications Figure 26. LXT98x3 Package Specifications 208-Pin Plastic Quad Flat Package • Part Numbers: LXT9883HC, LXT9863HC • Commercial Temperature Range ( ...