LTC1344AIG Linear Technology, LTC1344AIG Datasheet - Page 8

IC TERMINATOR CABLE MULTI 24SSOP

LTC1344AIG

Manufacturer Part Number
LTC1344AIG
Description
IC TERMINATOR CABLE MULTI 24SSOP
Manufacturer
Linear Technology
Type
Cabler
Datasheet

Specifications of LTC1344AIG

Number Of Terminations
6
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC1344AIG
Manufacturer:
LT/凌特
Quantity:
20 000
Part Number:
LTC1344AIG#PBF
Manufacturer:
LTC
Quantity:
109
Part Number:
LTC1344AIG#PBF
Manufacturer:
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Quantity:
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APPLICATIONS
LTC1344A
if the receiver input impedance is on the low side. All of
Linear Technology’s V.35 receivers meet the RS485 input
impedance specification as shown in Figure 11, which
insures compliance with the V.35 specification when used
with the LTC1344A.
8
Z
GENERATOR
Figure 11. V.35 Receiver Using the LTC1344A
A
B
C
50
50
ON
S1
–0.8mA
Figure 10. Typical V.35 Interface
125
51.5
51.5
–7V
U
ON
S2
INTERCONNECTING
A
B
C
LTC1344A
124
BALANCED
INFORMATION
CABLE
U
–3V
I
B
C
A
Z
'
'
'
TERMINATION
3V
W
125
Z
Z
CABLE
RECEIVER
50
50
LOAD
V.35
12V
RECEIVER
1mA
V
U
1344 F11
Z
1344 F10
The generator differential impedance must be 50
150
and B to ground C must be 150
termination, switches S1 and S2 are both on and the top
side of the center resistor is brought out to a pin so it can
be bypassed with an external capacitor to reduce common
mode noise as shown in Figure 12.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
The LATCH Pin
The LATCH pin (21) allows the select lines (M0, M1, M2
and DCE/DTE) to be shared with multiple LTC1344As,
each with its own LATCH signal. When the LATCH pin is
held low the select line input buffers are transparent. When
the LATCH pin is pulled high, the select line input buffers
latch the state of the Select pins so that changes on the
select lines are ignored until LATCH is pulled low again. If
the latch feature is not used, the LATCH pin should be tied
to ground.
and the impedance between shorted terminals A
Figure 12. V.35 Driver Using the LTC1344A
DRIVER
V.35
LTC1344A
124
15 . For the generator
51.5
C1
100pF
51.5
S2
ON
S1
ON
1344 F12
A
B
C
to

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