PDI1394P23BD ST-Ericsson Inc, PDI1394P23BD Datasheet - Page 35

• Manufacturer Part Number: PDI1394P23BD
• Description: IC IEEE 1394 LINK CTRLR 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394P23BD

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 64-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Normal operation. Interface is operating normally, with LPS
2. LPS deasserted. The LLC deasserts the LPS signal and, within
3. Interface reset. After T
Philips Semiconductors
The sequence of events for resetting the PHY-LLC interface when it
is in the nondifferentiated mode of operation (ISO terminal is high) is
as follows:
2001 Sep 06
2-port/1-port 400 Mbps physical layer interface
asserted, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line. In the above diagram, the LPS signal is shown
as a non-pulsed level signal. However, it is permissible to use a
pulsed signal for LPS in a direct connection between the PHY
and LLC; a pulsed signal is required when using an isolation
barrier (whether of the Philips Bus Holder type or Annex J type).
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
CTL0, CTL1
SYSCLK
D0 – D7
LREQ
LPS
ISO
LPS_RESET
(low)
T
LPSL
time, the PHY determines that
T
LPSH
(a)
Figure 22. Interface Disable, ISO Low
(b)
T
LPS_RESET
35
4. Interface restored. After the minimum T
stated above for interface reset, but also stops SYSCLK activity. The
If the LLC continues to keep the LPS signal deasserted, it requests
that the interface be disabled. The PHY disables the interface when
it observes that LPS has been deasserted for T
the interface is disabled, the PHY sets its CTL and D outputs as
interface is also placed into the disabled condition upon a hardware
reset of the PHY. The timing for interface disable is shown in
Figure 22 and Figure 23.
When the interface is disabled, the PHY will enter a low-power state
if none of its ports is active.
may again assert LPS active. (The minimum T
provides sufficient time for the biasing networks used in Annex J
type isolation barrier circuits to stabilize and reach a quiescent
state if the isolation barrier has somehow become unbalanced.)
When LPS is asserted, the interface will be initialized as
described below.
T
LPS_DISABLE
(c)
RESTORE
(d)
PDI1394P23
LPS_DISABLE
RESTORE
time, the LLC
Preliminary data
SV01812
interval
. When