DP83816AVNG/NOPB National Semiconductor, DP83816AVNG/NOPB Datasheet - Page 27

• Manufacturer Part Number: DP83816AVNG/NOPB
• Description: IC MEDIA ACCESS CTRLR 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG/NOPB

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• For Use With: DP83816-MAAP - BOARD EVALUATION DP83816
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83816AVNG; *DP83816AVNG/NOPB; DP83816AVNG

3.0 Functional Description
3.11.5 Jabber Function
The jabber function monitors the DP83816's output and
disables the transmitter if it attempts to transmit a packet of
longer than legal size. A jabber timer monitors the
transmitter and disables the transmission if the transmitter
is active for approximately 20-30 ms.
Once disabled by the jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's
internal transmit enable is asserted. This signal has to be
de-asserted for approximately 400-600 ms (the “unjab”
time) before the jabber function re-enables the transmit
outputs.
The Jabber function is only meaningful in 10BASE-T mode.
3.11.6 Automatic Link Polarity Detection
The
incorporates an automatic link polarity detection circuit.
When seven consecutive link pulses or three consecutive
receive packets with inverted End-of-Packet pulses are
received, bad polarity is reported.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
The bad polarity condition is latched. The DP83816's
10BASE-T transceiver module corrects for this error
internally and will continue to decode received data
correctly. This eliminates the need to correct the wiring
error immediately.
3.11.7 10BASE-T Internal Loopback
When the LOOPBACK bit in the BMCR register is set,
10BASE-T transmit data is looped back in the ENDEC to
the receive channel. The transmit drivers and receive input
circuitry are disabled in transceiver loopback mode,
isolating the transceiver from the network.
Loopback is used for diagnostic testing of the data path
through the transceiver without transmitting on the network
or being interrupted by receive traffic. This loopback
function causes the data to loopback just prior to the
10BASE-T output driver buffers such that the entire
transceiver path is tested.
3.11.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83816, as the required signal conditioning is integrated
into the device.
Only
matching resistors are required for the 10BASE-T transmit
and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated by at least 30 dB.
3.11.9 Transmitter
The encoder begins operation when the transmit enable
input to the physical layer is asserted and converts NRZ
data
transceiver. For the duration of assertion, the serialized
transmit data is encoded for the transmit-driver pair (TD±).
The last transition is always positive; it occurs at the center
of the bit cell if the last bit is a one, or at the end of the bit
cell if the last bit is a zero.
3.11.10 Receiver
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
to
isolation/step-up
DP83816's
pre-emphasized
10BASE-T
transformers
Manchester
transceiver
(Continued)
and
data
impedance
for
module
the
27
clock signals and data. The differential input must be
externally terminated with a differential 100Ω termination
network to accommodate UTP cable. The internal
impedance of RD± (typically 1.1KΩ) is in parallel with two
54.9Ω resistors to approximate the 100Ω termination.
The decoder detects the end of a frame when no more mid-
bit transitions are detected.
3.11.11 Far End Fault Indication
Auto-Negotiation provides a mechanism for transferring
information from the Local Station to the Link Partner that a
remote fault has occurred for 100BASE-TX.
A remote fault is an error in the link that one station can
detect while the other cannot. An example of this is a
disconnected fiber at a station’s transmitter. This station will
be receiving valid data and detect that the link is good via
the Link Integrity Monitor, but will not be able to detect that
its transmission is not propagating to the other station.
If three or more FEFI IDLE patterns are detected by the
DP83816, then bit 4 of the Basic Mode Status register is
set to one until read by management, additionally bit 7 of
the PHY Status register is also set.
The first FEFI IDLE pattern may contain more than 84 ones
as the pattern may have started during a normal IDLE
transmission which is actually quite likely to occur.
However, since FEFI is a repeating pattern, this will not
cause a problem with the FEFI function. It should be noted
that receipt of the FEFI IDLE pattern will not cause a
Carrier Sense error to be reported.
If the FEFI function has been disabled via FEFI_EN (bit 3)
of the PCSR Configuration register, then the DP83816 will
not send the FEFI IDLE pattern.
3.12 802.3u MII
The DP83816 incorporates the Media Independent
Interface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices. This section describes the MII configuration steps
as well as the serial MII management interface and nibble
wide MII data interface.
3.12.1 MII Access Configuration
The DP83816 must be specifically configured for
accessing the MII. This is done by first connecting pin 133
(MD1/CFGDISN) to GND through a 1KΩ resistor. Then
setting bit 12 (EXT_PHY) of the CFG register (offset 04h)
to 1. See Section 4.2.2. When this bit is set, the internal
Phy is automatically disabled, as reported by bit 9
(PHY_DIS) of the CFG register. The MII must then be
initialized, as described in Section 3.12.4, before the
external PHY can be detected.
If external MII is not selected through the register setting as
described, then the internal Phy is used and the MII pins of
the MacPhyter-II can be left unconnected.
3.12.2 MII Serial Management
The MII serial management interface allows for the
configuration and control of PHY registers, gathering of
status, error information, and the determination of the type
and capabilities of the attached PHY(s).
The MII serial management specification defines a set of
thirty-two 16-bit status and control registers that are
accessible through the management interface pins MDC
and MDIO. A description of the serial management
interface access and access protocol follows.
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