KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet

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Device TC1797 Marking/Step EES-AC, ES-AC, AC Package P/PG-BGA-416-10 01710AERRA This Errata Sheet describes the deviations from the current user documentation. Table 1 Current Documentation TC1797 User’s Manual TC1797 Data Sheet TriCore 1 Architecture Make sure you always use the corresponding ...

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D: Documentation Update • Number: ascending sequential number within the three previous fields. As this sequence is used over several derivatives, including already solved deviations, gaps inside this enumeration can occur. Note: Devices marked with EES or ES are ...

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History List / Change Summary Table 2 History List Version Date 1.0 22.09.2008 1.1 04.12.2008 1.2 01.07.2009 1.3 18.12.2009 Note: Changes to the previous errata sheet version are particularly marked in column “Change” in the following tables. Table 3 ...

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Table 4 Functional Deviations Functional Short Description Deviation BCU_TC.006 Polarity of Bit SVM in Register ECON BROM_TC.005 Power-on reset (PORST) while no external clock is available CPU_TC.105 User / Supervisor mode not staged correctly for Store Instructions CPU_TC.106 Incorrect PSW ...

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Table 4 Functional Deviations (cont’d) Functional Short Description Deviation DMI_TC.016 CPU Deadlock possible when Cacheable access encounters Flash Double-Bit Error DMI_TC.017 DMI line buffer is not invalidated by a write to OVC_OCON.DCINVAL if cache off. EBU_TC.020 BAA Delay Options Controlled ...

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Table 4 Functional Deviations (cont’d) Functional Short Description Deviation FlexRay_AI.070 Cycle counter MTCCV.CCV is updated erroneously in dedicated startup states FlexRay_AI.071 Faulty update of LDTS.LDTA, LDTB[10:0] due to parity error FlexRay_AI.072 Improper resolution of startup collision FlexRay_AI.073 Switching from loop-back ...

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Table 4 Functional Deviations (cont’d) Functional Short Description Deviation FlexRay_AI.083 Irregular sync frame list exported in state Coldstart_Gap FlexRay_AI.084 Corruption of frame received in slot N by second frame reception before action point FlexRay_AI.085 Cycle filtering in slot 1 FlexRay_AI.086 ...

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Table 4 Functional Deviations (cont’d) Functional Short Description Deviation OCDS_TC.016 Triggered Transfer dirty bit repeated by IO_READ_TRIG OCDS_TC.018 Startup to Bypass Mode requires more than five clocks with TMS=1 OCDS_TC.020 ICTTA not used by Triggered Transfer to External Address OCDS_TC.021 ...

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Table 4 Functional Deviations (cont’d) Functional Short Description Deviation RESET_TC.001 SCU_RSTSTAT.PORST not set by a combined Debug / System / Application Reset SCU_TC.016 Reset Value of Registers ESRCFG0/1 SSC_AI.022 Phase error detection switched off too early at the end of ...

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Table 6 Application Hints Hint Short Description ADC_AI.H002 Minimizing Power Consumption of an ADC Module CPU_TC.H004 PCXI Handling Differences in TriCore1.3.1 EBU_TC.H005 Potential live-lock situation on concurrent CPU and PCP accesses to external memories EBU_TC.H008 Use of EBU standby mode ...

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Table 6 Application Hints (cont’d) Hint Short Description MultiCAN_TC.H003 Message may be discarded before transmission in STT mode MultiCAN_TC.H004 Double remote request OCDS_TC.H001 IOADDR may increment after aborted IO_READ_BLOCK OCDS_TC.H002 Setting IOSR.CRSYNC during Application Reset OCDS_TC.H003 Application Reset during host ...

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Table 6 Application Hints (cont’d) Hint Short Description SSC_TC.H003 Handling of Flag STAT.BSY in Master Mode TC1797, EES-AC, ES-AC, AC History List / Change Summary 12/101 Errata Sheet Cha Pa nge ge 101 Rel. 1.3, 18.12.2009 ...

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Functional Deviations BCU_TC.006 Polarity of Bit SVM in Register ECON The polarity of bit SVM (State of FPI Bus Supervisor Mode Signal) in the SBCU Error Control Capture register SBCU_ECON is inverted compared to its description in the User’s ...

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Unlike attributes derived from the instruction, the User/Supervisor mode status of TriCore initiated bus transactions is not staged correctly in the TriCore pipeline and is derived directly from the PSW.IO bit field. This issue can only cause a problem in ...

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In this case, the PSW user status bits are updated with the value from the IP instruction rather than the later MTCR instruction. This situation only occurs in 2 cases: • MUL/MADD/MSUB instruction followed by ...

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FCX and LCX, thus achieving similar functionality to the SYSCON.FCDSF flag. In the case where the CSA list is dynamically managed, no reliable workaround is possible. CPU_TC.108 Incorrect Data Size for Circular Addressing mode instruc- tions with ...

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Example ... LDA a8, 0xD000000E ; Address of un-aligned load LDA a12, 0xD0000820 ; Circular Buffer Base LDA a13, 0x00180014 ; Circular Buffer Limit and Index ... ld.w d6, [a8] add d4, d3, d2 st.d [a12/a13+c], d0/d1 ; Circular Buffer ...

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Note: In the current TriCore1 CPU implementation, load accesses are initiated from the DEC pipeline stage whilst store accesses are initiated from the following EXE pipeline stage. To avoid memory port contention problems when a load follows a store instruction, ...

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LDRAM. The double-word load encounters the circular buffer wrap condition and should be split into 2 word accesses, to the top and ...

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The CPU store buffer contains a byte store instruction, st.b, targeting the base address + 0x1 of a circular buffer. • A word load instruction, ld.w, is executed using circular addressing mode, targetting the same circular buffer as the ...

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In systems with an enabled MMU and where either the store buffer or load instruction targets an address undergoing PTE-based translation, the conflict detection is just performed on address bits (9:0), since higher order ...

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CPU store buffer. The word load instruction encounters the circular buffer wrap condition and is split into 2 half-word accesses, to the top (0xD0001012) and bottom (0xD0001000) of the circular buffer. The first load access completes correctly, but, ...

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However, due to the bug longer straight- forward to discriminate FCU traps from other context management (Class 3) traps. Since the read ...

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Now read valid D15 to obtain TIN ... Since the initial contents of the upper context registers are unknown necessary to check one of the upper context registers twice, with different values, ...

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CPU_TC.113 Interrupt may be taken during Trap entry sequence A problem exists whereby interrupts are not correctly disabled at the very beginning of a trap entry sequence, and under certain circumstances an interrupt may be taken at the start of ...

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Unfortunately, with this issue that premise no longer holds - the code interrupted and state saved in a CSA can be that of a privileged trap handler. Dealing with this changed circumstance is easy, provided it is considered ...

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Call / Branch to NMI handler based on d13 result > Note that this code segment assumes that the BTV CSFR is static during runtime. If this is not the case then ...

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CSA into memory dsync sh.h d14, d15, #12 insert d15, d14, d15, #6, #16 mov.a a15, d15 ; load trap value of d15 from CSA ld.w d15, [a15]0x3C mov.a a15, a11 movh.a a11, #@his(interuptReal) lea a11, [a11]@los(interruptReal) ; ...

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After execution of the UPDFL instruction, one or more of the PSW[31:26] bits are set - either the PSW bit(s) are set by UPDFL or were set prior to execution and not cleared by the UPDFL instruction. • FPU ...

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Halt mode, or where interrupts are temporarily enabled during Halt mode. In this case an interrupt may be latched whilst the CPU is in Halt mode, and subsequently disabling interrupts during Halt mode, by ...

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If the debugger action is to re-start normal execution, the interrupt enable status should be restored from the value read upon hitting the initial breakpoint and the CPU re-started. DMA_TC.013 DMA-LMB-Master Access to Reserved Address Location DMA-LMB-Master goes into an ...

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The following should be noted: • At all times the DMA-FPI-Master and DMA-FPI-Slave remain accessible. • If the LMB-DMA-Master is in the lock-up state then accesses can still be made to the LMB bus by all other LMB-Masters (e.g. LFI-LMB-Master). ...

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If the system has a data cache, the data cache must be used to cache read- only data only (such as Flash contents). Writes to cacheable locations must not be used with the Data Cache enabled. Note that this ...

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LMB masters in the 2KByte DCache configuration, this would affect debuggers. Hence it would only be possible to view this memory space in a debugger if it takes appropriate steps to make the memory region accessable (e.g. by temporarily ...

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DMI LMB master and the CPU become deadlocked. This situation would then only be recoverable by a Watchdog reset. The problem exists within the DMI DLB, which is used as a single cache line when no data cache ...

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OVC_OCON.DCINVAL bit to ensure coherency between the DMI and background memory. It should be noted that this problem is not encountered when the D-cache is turned on. When OVC_OCON.DCINVAL will correctly invalidate ...

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Cachei operand is random non- protected cacheable address. cachei.wi [a0] of the value in a0. If the user is not concerned in invalidating the DMI line buffer but simply guaranteeing its coherency with external memory then ...

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EBU_TC.021 Incorrect delay calculation accessing Asynchronous mem- ories The EBU has the facility for the flash clock to run continuously by setting one of the BUSRCONx.BFCMSEL to 0 same clock, then all accesses requiring a flash clock will use the ...

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This results in the timing detailed in the table below, where CP1 is the first clock cycle of the command phase, DHn is the last clock cycle of the Data Hold Phase and T is one period of the EBU ...

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The correct behavior would be a reload when the requested conversion (of channel_2) is started. Therefore the start of conversion for channel_2 is delayed by maximum one conversion-time. After this delay it will be continued with equidistant conversion- starts. Please ...

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FIRM_TC.010 Data Flash Erase Suspend Function This problem affects devices with microcode version V11 (see FIRM_TC.H000 for identification of the microcode version): A sector DFx in the Data Flash may not be correctly erased when two successive erase operations are ...

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Erase DFx 5. Concurrent programming of DFy may be triggered. Workaround 2 After starting the erase of Data Flash sector DFx, delay the start of the programing of sector DFy by at least 250 ms, e.g.: 1. Erase DFx ...

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Table 8 Flash erase timings as per spec. Flash P-Flash, 2 MByte D-Flash, 64 Kbyte [Both Data Flash] Flash erase timings measured on actual device are as below Table 9 Actual Flash erase timings. Flash P-Flash, 2 MByte D-Flash, 64 ...

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Table 10 Relative erase time increments. Frequency[MHz] 150 180 FLASH_TC.035 Flash programing time out of specification As per specification flash programing time specified is per page 5msec Where as actual programing time measured on the device is per page 5.5msec ...

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FlexRay_AI.062 Sync frame reception after noise or aborted frame before action point Description: In case noise or an aborted frame leads to the detection of a secondary time reference point (STRP) and after this a valid sync frame is detected ...

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Scope: The erratum is limited to the case where a non sync frame is received in one slot and a sync frame is received in the following slot. Additionally, the detection of valid frame for the non sync frame has ...

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Workaround Avoid faulty configurations with more than gSyncNodeMax nodes configured to be transmitter of sync frames. FlexRay_AI.066 Time stamp of the wrong channel may be used for offset correction term Description: In case the temporal deviation (= time between primary ...

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Therefore, the error of the local time caused by the implementation error is also minimized. FlexRay_AI.067 Reception of more than gSyncNodeMax different ...

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FlexRay_AI.069 Update of Aggregated Channel Status ACS in dynamic segment in minislots following slot ID 2047 Description: In case the slot counter has reached ID 2047 and the end of dynamic segment is not reached, the slot counter wraps around ...

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Leading coldstart node: cycle ’no schedule’ at POC-state ’coldstart collision resolution’ • Following coldstart node: cycle 1 at POC-state ’integration coldstart check’ • Integrating node: cycle 1 at POC-state ’integration consistency check’ Effects: MTCCV.CCV is updated with the correct ...

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FlexRay_AI.072 Improper resolution of startup collision Description: In case a CAS symbol is received during startup exactly at the beginning of cycle 0, the detection of following startup frames is not possible. Scope: The erratum is limited to the case ...

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Effects: The error interrupt flag EIR.MHF is raised and the contents of the first received non-null frames will be lost. Workaround Run loop-back tests with 10 MBit/s (PRTC1.BRP[1: hardware reset after a loop-back test. FlexRay_AI.074 Integration successful on ...

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Scope: The erratum is limited to the case of simultaneous generation of internal signals ’integration successful on X’ on one channel and ’integration abort Y’ on the other channel. Effects: In the described cases the E-Ray either is stuck in ...

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Workaround None. FlexRay_AI.076 CCSV.SLM [1:0] delayed to CCSV.POCS[5:0] on tran- sitions between states WAKEUP and READY. Description: When the POC state changes between WAKEUP and READY the content of register CCSV may show a slight discontinuity, i.e. CCSV.SLM [1:0] may ...

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Effects: The wakeup pattern is transmitted n bit times early. Workaround Set gdWakeupSymbolRxLow to value >= 11. FlexRay_AI.078 Payload corruption after reception of valid frame fol- lowed by slot boundary crossing frame Description: If after reception of a valid frame ...

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The transfer of a received valid frame from TBF to MBF is initiated by the end of the actual slot. Execution is started not later than 40 bclk periods after the slot change. 40 bclk periods equate 10 bit times, ...

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Workaround Write 0x00000000 to any address of IBF directly before applying CLEAR_RAMS command. FlexRay_AI.081 Write accesses to ERAY_NDIC* and ERAY_MSIC* can fail if ERAY_CLC.FMC >= 2 Description: The Registers NDIC1 - NDIC4 and MSIC1 - MSIC4 are only accessible if ...

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Detection of WUP is independent of WakeupSymbolRxWindow’s phase. Workaround None. FlexRay_AI.083 Irregular sync frame list exported in state Coldstart_Gap Description: If the protocol engine is in the state Coldstart_Gap, it stops transmitting its own startup frame (according to the protocol ...

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Case3: Frame reception starts in slot N+1. Scope: The erratum is limited to the case where a receive slot is followed by a transmit slot and where at least the complete header of another frame is received before the frame ...

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The erratum is limited to the case where two (or more) message buffers are configured for slot 1 and cycle filtering is used. Effects running message buffer scan is interrupted by the NIT it cannot be guaranteed that ...

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If the status of IBF1PAG has changed from the first to the second read access, IBF1 is accessible, otherwise IBF2 is accessible (and vice versa). FlexRay_AI.088 A sequence of received WUS may generate redundant SIR.WUPA/B events Description sequence ...

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The erratum is limited to the case of receiving too few sync frames for rate correction calculation (SyncCalcResult=MISSING_TERM in an odd cycle). Effects: In the described case a rate correction value of zero is applied in NORMAL_ACTIVE / NORMAL_PASSIVE state ...

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Workaround Avoid configurations with pMicroInitialOffsetA,B equal to zero. If the related configuration constraint pMicroInitialOffsetA,B ...

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FlexRay_AI.094 Sync frame overflow flag EIR.SFO may be set if slot counter is greater than 1024 Description the static segment the number of transmitted and received sync frames reaches gSyncNodeMax and the slot counter in the dynamic segment ...

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Scope: The erratum is limited to the case where the calculated rate correction value is in the range of [-pClusterDriftDamping .. +pClusterDriftDamping]. Effects: The displayed rate correction value RCV.RCV[11: the range of [- pClusterDriftDamping .. +pClusterDriftDamping] instead of ...

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In the described case the faulty node may not stop slot counting and may continue to transmit dynamic frames. This may lead to a frame collision in the current dynamic segment. Workaround None. FlexRay_AI.097 Loop back mode operates only at ...

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Workaround There is no workaround available. Attention: Do not assert restart for longer periods of time unless the interface shall be functionally “locked”. The bug-fixed version of future devices will also reset DAP as long as restart is asserted, but ...

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Do not use the DAP telegrams jtag_setIR and jtag_swapIR with n less than eight. • Use the CRC protected DAP interface if the application environment may cause transmission errors on the JTAG signals. OCDS_TC.014 Triggered Transfer does not support ...

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The dirty bit is therefore cleared after each IO_READ_WORD. A consecutive IO_READ_TRIG instruction however IO_READ_WORD will then again see a set dirty bit even if no trigger was missed. Workaround Do not ...

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Workaround No workaround in “Triggered Transfer to External Address” mode possible, only the fixed address xx10F068 In “Internal Mode” however ICTTA is working as specified, so for certain use cases the intended DMA functionality can be activated by a code ...

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OCDS_TC.024 Loss of Connection in DAP three-pin Mode Devices of the Audo Future family allow tool access via dedicated pins in two basic protocol modes: DAP and JTAG. To avoid changes to the application environment, the tool selects the protocol ...

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OCDS_TC.025 PC corruption when entering Halt mode after a MTCR to DBGSR In cases where the CPU is forced into HALT mode by a MTCR instruction to the DBGSR register, there is a possibility of PC corruption just before HALT ...

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After the RFM, the CPU should resume execution at the point where it left it when the breakpoint happened.On execution of the RFM instruction, a light-weight debug context is restored ...

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OCDS_TC.027 BAM breakpoints with associated halt action can poten- tially corrupt the PC. BAM breakpoints can be programmed to trigger a halt action. When such a breakpoint is taken the CPU will go into HALT mode immediately after the instruction ...

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PCP_TC.023 JUMP sometimes takes an extra cycle Following a taken JUMP, the main state machine may misleadingly take an additional cycle of pause. This occurs if the already prefetched next or second next instruction after the JUMP is one of ...

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Workaround Keep the FPI time-out setting as high as possible and do not include long sequences of back to back atomic PRAM instructions the highest amount of back to back atomic PRAM instructions in any PCP channel ...

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PCP_TC.036 Unexpected behaviour after failed posted FPI write If PCP posts an FPI write (including those in atomic FPI operations) which produces an FPI error, following malfunctions may be observed: • The PCP may lock the FPI bus • Improper ...

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If atomicity is not required, either: • ensure that no FPI master (including PCP itself) issues an FPI RMW operation on PRAM, or • replace all MSET.PI, MCLR.PI and XCH.PI with their non-atomic equivalents. Equivalent non-atomic instructions: • MSET.PI OR.PI ...

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PCP 2:1 mode is enabled, • PCP is configured to post error interrupts to CPU, • a channel is running, • this channel’s R7.CEN is cleared, • PCP exits this channel with posting an interrupt to the CPU, • ...

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If bit field SCU_RSTSTAT.ESR0 needs to contain a value different from 00 instead of checking SCU_RSTSTATCB0, SCU_RSTSTATCB1, and SCU_RSTSTATCB3 should be checked to be set. SCU_TC.016 Reset Value of Registers ESRCFG0/1 The reset value of register SCU_ESRCFG0 is 0x00000100 (instead ...

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SSC_AI.023 Clock phase control causes failing data transmission in slave mode If SSC_CON. and no leading delay is issued by the master, the data output of the slave will be corrupted. The reason is that the chip select ...

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Workaround Use at least one leading delay in order to avoid this problem. SSC_AI.026 Master with highest baud rate set generates erroneous phase error If the SSC is in master mode, the highest baud rate is initialized and CON.PO = ...

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Deviations from Electrical- and Timing Specification DTS_TC.P001 Test Conditions for Sensor Accuracy T Parameter “Sensor Accuracy” (symbol T is verified by design / characterization. The corresponding note will be added in the next revisions of the Data Sheet. FADC_TC.P003 ...

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Application Hints ADC_AI.H002 Minimizing Power Consumption of an ADC Module For a given number of A/D conversions during a defined period of time, the total energy (power over time) required by the ADC analog part during these conversions via ...

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Several previous inconsistencies regarding the updating of the PCXI and the storing of PCXI fields in the first word of a CSA are now removed. • CALL has always placed the full PCXI into the CSA • BISR has always ...

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Method #2 For applications where the time prior to execution of the BISR instruction is critical, the priority number of the interrupted task may be read from the CSA pointed to by the PCXI after execution of the BISR ...

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Workaround In case that several masters have access to the EBU, the application software has to reserve time windows for each of the masters, whose duration depends on the latency constraints of the application. EBU_TC.H008 Use of EBU standby mode ...

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Workaround This error condition is avoided by increasing the address phase length or by adding another access phase (i.e. address hold, command delay or ...

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FlexRay_AI.H003 Select upper-/lower page for IBF1/IBF2 in RAM test mode Each input buffer (IBF1/IBF2) consists of upper and lower page with 64 entries each. These pages can be selected via page select register (CUST1.IBF1PAG, CUST1.IBF2PAG). Due to IBFS is not ...

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FPI_TC.H001 FPI bus may be monopolized despite starvation protection During a sequence of back to back 64-bit writes performed by the CPU to PCP memories (PRAM/CMEM) the LFI will lock the FPI bus and no other FPI master (PCP, DMA, ...

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SDI line low level at the end of the last stop bit time slot (e.g. when the SDI line is permanently held low). Therefore, make sure that the ...

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Workaround In case of reset, or ,if switching off then on the LVDS pad by software, the PDR register should be programmed soonest possible for the LVDS pads to reach its stable level. User has to take care that the ...

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MultiCAN_TC.H002 Double Synchronization of receive input The MultiCAN module has a double synchronization stage on the CAN receive inputs. This double synchronization delays the receive data by 2 module clock cycles. If the MultiCAN is operating at a low module ...

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There will, however, not be more data frames than there are corresponding remote requests ltiC A N Figure 3 Loss ...

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A monitor program may be confused by this and drop out of the higher level communication protocol, especially if the host posts an instruction (with the IO_WRITE_WORD instruction) after detecting the reset. Workaround Two correlated activities should be incorporated ...

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OCDS_TC.H004 Device Identification by Application Software While each device type can easily be recognized by test equipment using the JTAG ID, over the years each device family has had a proprietary way to provide the same information to application software ...

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Workaround Ensure that there are no PRAM locations with an incorrect parity bit by initialising every PRAM location (with parity checking enabled) prior to enabling trapping of PRAM parity errors. PCP_TC.H005 Unexpected parity errors when address 0 of CMEM is ...

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PORTS_TC.H004 Using LVDS Ports in CMOS Mode The following constraint applies to an LVDS pair used in CMOS mode: Only one pin of a pair shall be used as output, the other shall be used as input. Using both pins ...

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Table 12 Worst Case Power-up Cross Current > 0.5 V don’t care < 0.5 V < 0.8 V < 0.5 V 0.8 V < V < 0 3.6 V Even under worst case conditions, this ...

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SSC_AI.H002 Transmit Buffer Update in Master Mode during Trailing or Inactive Delay Phase When the Transmit Buffer register TB is written in master mode after a previous transmission has been completed, the start of the next transmission (generation of SCLK ...

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It is therefore recommended to update the Transmit Buffer in slave mode after the transmit interrupt (TIR) has been generated (i.e. after the first SCLK phase). After reset, the Transmit Buffer may be written at any time. SSC_TC.H003 Handling of ...