SI5041-EVB Silicon Laboratories Inc, SI5041-EVB Datasheet - Page 5

• Manufacturer Part Number: SI5041-EVB
• Description: BOARD EVAL FOR SI5041
• Manufacturer: Silicon Laboratories Inc
• Series: -r
• Type: Transceiverr

Specifications of SI5041-EVB

• Frequency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: SI5041

1.4. Reference Clock Details
The Si5041 can function without a reference clock and
meet all system jitter generation and jitter tolerance
specifications. However, the presence of a reference
clock provides the following capabilities:


A reference clock to the Si5041 can be input from an
external source, or it can be generated from the
onboard Si534. Since the clock from the Si534 is
linearly summed with the external reference clock input,
care must be taken to ensure that both clock sources
are not active at the same time. When the Si534 is
enabled (JP16 on), its output will be present at SMAs J1
and J5 for monitoring and/or system usage. When the
Si534 is OFF, a differential clock applied at J1 and J5
will be attenuated by 2.7 dB before it reaches the
REFCLK± inputs of the Si5041.
While an Si534 has the capability of generating any four
frequencies between 10 MHz and 1400 MHz, this Si534
has been programmed to generate four specific
frequencies. Jumpers JP17 and JP18 control the
FS[1:0] inputs to the Si534 (see Figure 6). The four
frequencies are as follows:


Ability to measure the frequency error of the input
data and generate a Loss-of-Lock indication if the
frequency error exceeds 1000 ppm with respect to
the reference clock.
Only acquire lock if the input data is within 200 ppm.
155.52000 MHz Set FS[1:0] = 00
This is 1/64 of the SONET OC-192 rate of
9.95328e9 bps
161.13281 MHz Set FS[1:0] = 01
This is 1/64 of the 10 GIGE LAN PHY rate of
10.3125e9 bps
Figure 7. Synchronous Test Clock
Rev. 0.1


While the Si534 output is clean enough to meet the XFP
requirements for the "optional clean reference clock",
the Si5040 does not support this function. Please look
at the Si5041 if you desire this function.
1.5. RD De-Emphasis
Even though the output data at the Si5041 RD pins has
very fast transitions, we have found that some
customers prefer some signal shaping of the RD output
signal at the XFI. Therefore, the Si5041 EVB has a de-
emphasis circuit added to the RD± outputs that is not
shown in the schematic of Figure 10. This circuit is
composed of a few resistors and capacitors, all of which
can be generic, low-cost units. Because it is a passive
circuit, it slightly attenuates the RD signal, which
requires that the RD signal level from the Si5041 be
slightly increased. Please use the Si5041 Register 56 to
increase the RD drive signal from its default value of
600 mV to 800 mV. See the Si5041 data sheet for more
information. The circuit that is implemented on the EVB
is shown below:
Within an XFP module, the pre-emphasis circuit should
be located as close to the Si5041 RD± pins as is
practical. In an XFP module, the pre-emphasis circuit
above can be modified to remove one component yet
still behave the same electrically. The following circuit
shows this simplification.
167.33165 MHz Set FS[1:0] = 10
This is 1/64 of the SONET OC-192 rate with 255/237
FEC overhead (10.709225e9 bps)
173.37075 MHz Set FS[1:0] = 11
This is 1/64 of the 10 GIGE LAN Phy rate with 255/
237 FEC overhead (11.095727e9 bps)
5041
RD-
5041
RD+
Figure 8. EVB De-Emphasis Circuit
3.0 pF
3.0 pF
20.5
20.5
Si5041-EVB
.01 µF
274 
274 
.01 uF
XFI RD-
XFI RD+
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