DS1990R-F5 Maxim Integrated Products, DS1990R-F5 Datasheet - Page 7

• Manufacturer Part Number: DS1990R-F5
• Description: Serial Number Registration
• Manufacturer: Maxim Integrated Products

Specifications of DS1990R-F5

• Lead Free Status / Rohs Status: No

DS1990R: Serial Number iButton
1-Wire SIGNALING
The DS1990R requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on
one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except
for the presence pulse the bus master initiates all these signals.
To get from idle to active, the voltage on the 1-Wire line needs to fall from V
to below V
. To get from active
PUP
ILMAX
to idle, the voltage needs to rise from V
to above V
. The time it takes for the voltage to make this rise, ref-
ILMAX
IHMIN
erenced as e in Figure 6, depends on the value of the pullup resistor (R
) and capacitance of the 1-Wire network
PUP
attached.
The initialization sequence required to begin any communication with the DS1990R is shown in Figure 6. A Reset
Pulse followed by a Presence Pulse indicates the DS1990R is ready to receive a ROM function command. If the
bus master uses slew-rate control on the falling edge, it must pull down the line for t
+ t
to compensate for the
RSTL
F
edge.
Figure 6. INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
t
e
MSP
V
PUP
V
IHMIN
V
ILMAX
0V
t
t
t
F
RSTL
PDL
t
t
PDH
REC
t
RSTH
RESISTOR
MASTER
DS1990R
After the bus master has released the line it goes into receive mode (RX). Now the 1-Wire bus is pulled to V
via
PUP
the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the V
is crossed, the DS1990R
IHMIN
waits for t
and then transmits a Presence Pulse by pulling the line low for t
. To detect a presence pulse, the
PDH
PDL
master must test the logical state of the 1-Wire line at t
.
MSP
READ/WRITE TIME SLOTS
Data communication with the DS1990R takes place in time slots, which carry a single bit each. Write-time slots
transport data from bus master to slave. Read-time slots transfer data from slave to master. The definitions of the
write and read-time slots are illustrated in Figure 7.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below
V
, the DS1990R starts its internal timing generator that determines when the data line will be sampled during a
ILMAX
write-time slot and how long data will be valid during a read-time slot.
MASTER-TO-SLAVE
For a write-one time slot, the voltage on the data line must have risen above V
after the write-one low time
IHMIN
t
is expired. For a write-zero time slot, the voltage on the data line must stay below V
until the write-zero
W1LMAX
ILMAX
low time t
is expired. For most reliable communication the voltage on the data line should not exceed V
W0LMIN
ILMAX
during the entire t
window. After the voltage has risen above V
, the DS1990R needs a recovery time t
W0L
IHMIN
REC
.
before it is ready for the next time slot
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