MAX1149BEUP Maxim Integrated Products, MAX1149BEUP Datasheet - Page 12

• Manufacturer Part Number: MAX1149BEUP
• Description: ADC / DAC Multichannel
• Manufacturer: Maxim Integrated Products

Specifications of MAX1149BEUP

• Lead Free Status / Rohs Status: No

Multichannel, True-Differential,
Serial, 14-Bit ADCs
The MAX1146–MAX1149 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy inter-
face to microprocessors (µPs). Figure 4 shows the typi-
cal application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
The MAX1146–MAX1149 analog input architecture con-
tains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
Figure 4. Typical Application Circuit
Figure 5. Functional Diagram
12
REFADJ
SHDN
SCLK
COM
2.2µF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
REF
CS
ANALOG
INPUTS
______________________________________________________________________________________
REGISTER
True-Differential Analog Input and
ANALOG
INPUT
INPUT
REFERENCE
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
COM
SHIFT
MUX
BANDGAP
+1.250V
AGND
MAX1148
MAX1149
DGND
CONTROL
Detailed Description
LOGIC
20kΩ
REFADJ
T/H
SSTRB
SHDN
DOUT
SCLK
V
DIN
CS
DD
A
V
IN
= 2.0V/V
0.1µF
0.01µF
INTERNAL
CLOCK
CLOCK
ADC
SAR
REF
4.7µF
MAX1149
OUT
10Ω
REGISTER
OUTPUT
SHIFT
Track/Hold
V
DD
V
I/O
SCK
I/O
MOSI
I/O
MISO
DD
µP
V
SS
DOUT
SSTRB
V
DGND
AGND
DD
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
C
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retain-
ing the charge on C
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF × (V
C
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is com-
plete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisi-
tion time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (t
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (R
mized to allow the T/H capacitance to charge within
this allotted time.
where R
R
and T/H switch resistances), and C
the sum of C
To minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
IN
T/H+
T/H+
is 2.6kΩ (which is the sum of the analog input MUX
and C
and C
SOURCE
t
ACQ
T/H+
T/H-
T/H-
= 11.5 × (R
is the analog input source impedance,
, C
track the analog input signal. At the
to the binary-weighted capacitive
T/H-
T/H+
ACQ
, and input stray capacitance).
) in which the T/H capacitance
SOURCE
and C
SOURCE
T/H-
+ R
IN
as a sample of the
) should be mini-
IN
is 18pF (which is
IN+
) × C
- V
IN
IN-
) from