DP83848IVV National Semiconductor, DP83848IVV Datasheet - Page 60

• Manufacturer Part Number: DP83848IVV
• Manufacturer: National Semiconductor

Specifications of DP83848IVV

• Lead Free Status / Rohs Status: Compliant

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7.2.11 CD Test and BIST Extensions Register (CDCTRL1)
15:8
Bit
7:6
1:0
5
4
3
2
BIST_CONT_MOD
10MEG_PATT_GA
BIST_ERROR_CO
CDPATTSEL[1:0]
CDPATTEN_10
RESERVED
RESERVED
Bit Name
Table 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B
UNT
E
P
Default
00, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RO
BIST ERROR Counter:
Counts number of errored data nibbles during Packet BIST. This
value will reset when Packet BIST is restarted. The counter sticks
when it reaches its max count.
RESERVED:
Must be zero.
Packet BIST Continuous Mode:
Allows continuous pseudo random data transmission without any
break in transmission. This can be used for transmit VOD testing.
This is used in conjunction with the BIST controls in the PHYCR
Register (0x19h). For 10Mb operation, jabber function must be dis-
abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1.
CD Pattern Enable for 10Mb:
1 = Enabled.
0 = Disabled.
RESERVED:
Must be zero.
Defines gap between data or NLP test sequences:
1 = 15 s.
0 = 10 s.
CD Pattern Select[1:0]:
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence
01 = Data, EOP1 sequence
10 = NLPs
11 = Constant Manchester 1s (10MHz sine wave) for harmonic dis-
tortion testing.
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Description