MAX5982CETE+ Maxim Integrated Products, MAX5982CETE+ Datasheet - Page 4

• Manufacturer Part Number: MAX5982CETE+
• Description: Power Switch ICs - POE / LAN PDIC, up to 70W
• Manufacturer: Maxim Integrated Products

Specifications of MAX5982CETE+

• Lead Free Status / Rohs Status: Details

IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with
ELECTRICAL CHARACTERISTICS (continued)
(V
voltages are referenced to V
T
Note 3: All devices are 100% production tested at T
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between V
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage, which takes V
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an
Figure 1. Effective Differential Input Resistance/Offset Current
4
A
LED Current Programmable
Range
LED Current with Grounded SL
LED Current Frequency
LED Current Duty Cycle
V
Internal Current Duty Cycle
Internal Current Enable Time
Internal Current Disable Time
SL Delay Time
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
IN
DD
= +25
______________________________________________________________________________________
= (V
Current Amplitude
DD
N
MAX5982A/MAX5982B/MAX5982C to exit power-on mode.
overload condition across V
PARAMETER
C.) (Note 3)
- V
SS
) = 48V, R
DET
SS,
= 24.9kω, R
unless otherwise noted. T
SYMBOL
DD
t
D
D
MPDO
f
I
t
I
ILED
T
VDD
MPS
OFFSET
IVDD
ILED
t
SL
SD
Integrated 70W High-Power MOSFET
and RTN.
I
INi + 1
I
INi
CLS
I
IN
= 615ω, and R
V
Normal and ultra-low-power sleep modes
Normal and ultra-low-power sleep modes
Normal sleep mode, V
Normal and ultra-low-power sleep modes
Ultra-low-power sleep mode
Ultra-low-power sleep mode
Time V
threshold to enter sleep and ultra-low-
power modes (MAX5982A)
T
T
I
OFFSET
J
J
SL
dR
rising
falling
A
DD
= 0V
i
=
= I
= +25NC. Limits over temperature are guaranteed by design.
(V
SL
(I
INi
below V
INi + 1
INi + 1
-
A
must remain below the SL logic
V
dR
INi
= T
i
- V
- I
INi
INi
CONDITIONS
V
J
)
SL
)
INi
ON
=
= -40
(I
= 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
INi + 1
shorter than or equal to t
1V
1V
N
LED
- I
C to +85
dR
INi
V
i
INi + 1
)
= 3.5V
N
C, unless otherwise noted. Typical values are at
V
IN
OFF_DLY
20.5
MIN
220
5.4
DD
10
10
80
and V
does not cause the
+150
TYP
24.5
250
228
SS
6.0
25
11
75
84
30
. See Figure 1.
MAX
28.5
12.2
236
6.6
20
88
UNITS
mA
mA
mA
ms
ms
Hz
NC
NC
%
%
s