HBLXT9785HE.C2 Intel, HBLXT9785HE.C2 Datasheet - Page 176

• Manufacturer Part Number: HBLXT9785HE.C2
• Manufacturer: Intel

Specifications of HBLXT9785HE.C2

• Lead Free Status / Rohs Status: Not Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 41
Table 63
Figure 42
Cortina Systems
SMII - 100BASE-FX Receive Timing
SMII - 100BASE-FX Receive Timing Parameters
SMII - 100BASE-FX Transmit Timing
®
RxData output delay from REFCLK
rising edge
RxData Rise/Fall Time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-
asserted
SYNC setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
REFCLK
RxData
SYNC
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TPFI
REFCLK
TxData
SYNC
TPFO
Parameter
t
3
t
1
t
5
t
2
Sym
t1
t2
t3
t4
t5
t6
t
t
3
6
Min
1.5
1.5
1.0
–
–
–
t
1
Typ1
18
23
–
1
–
–
t
1
t
2
Max
26
27
t
5
–
–
–
2
Units
BT
BT
ns
ns
ns
ns
2
2
t
6.0 Test Specifications
4
Minimum C
Maximum C
Synchronous
sampling of SMII
Synchronous
sampling of SMII
Test Conditions
–
–
–
L
L
Page 176
= 5 pF
= 20 pF