HI-8686PQI Holt Integrated Circuits, HI-8686PQI Datasheet - Page 3

• Manufacturer Part Number: HI-8686PQI
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8686PQI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: TQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION (cont.)
PROTOCOL DETECTION
The ARINC clock and One/Zero data that are derived from
the
Figure 3. The resulting steam of digital data is shifted into a
32-bit input register.
The ARINC clock and One/Zero data can also be created
from the TESTA and TESTB inputs as shown in Figure 4.
When either test input is high, the built-in analog line driver
is disabled.
For ARINC 561 operation, the TESTA and TESTB digital in-
put data streams must be derived from the ARINC 561 data,
clock and sync with external logic.
GAPCLK
RINA-10
RINB-10
PARITY
RESET
TESTA
TESTB
READ
RINA
RINB
digital
ENB
10KW
10KW
outputs of the built-in line receiver is illustrated in
DATABUS
TYPE
25KW
25KW
429
429
575
561
PROTECTION
RECEIVER
BIT PERIOD
LINE
ESD
&
69 - 133
69 - 133
69 - 133
(µs)
10
Table 1 - Typical Gap Detection Times
RXA
RXB
HOLT INTEGRATED CIRCUITS
Figure 1. Block Diagram
DETECT
CLOCK
DATA
MINIMUM GAP
&
HI-8685, HI-8686
310 - 599
310 - 599
103 - 200
(µs)
45
CLK
DATA
DETECT
DETECT
PARITY
COUNT
3
GAP
BIT
GAP DETECTION
The end of a data word is detected by an internal counter
that times out when a data One or Zero is not received for a
period equal to 16 cycles of the GAPCLK signal. The gap
detection time may vary between 16 and 17 cycles of the
GAPCLK signal since the incoming data and GAPCLK are
not usually synchronous inputs. The required frequency of
GAPCLK is a function of the mininum gap time specified for
the type of ARINC data being received. Table 1 indicates
typical frequencies that may be used for the various data
rates normally encountered.
GAP CLOCK
MHz
0.75
1.0
1.5
0.1
0.1
0.2
32-BIT
SHIFT
REG.
BIT 32
DETECT
ERROR
32
GAP DETECTION
21.3 - 22.7
10.7 - 11.3
TIME (µs)
BIT 32
RECEIVE
160 - 170
160 - 170
BUFFER
32-BIT
16 - 17
80 - 85
32
COUNT
BYTE
32-BIT
16-BIT
MUX
TO
16
DATA RDY
D0 - D15
ERROR