CY7C401-15DMB Cypress Semiconductor Corp, CY7C401-15DMB Datasheet - Page 8

• Manufacturer Part Number: CY7C401-15DMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C401-15DMB

• Density: 256Kb
• Word Size: 4b
• Sync/async: Asynchronous
• Expandable: Yes
• Package Type: DIP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

FIFO Expansion
Notes:
13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.
14. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data, and stays LOW
15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH
16. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH,
17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pin-compatible FIFOs from other manufacturers.
18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready
COMPOSITE
INPUT READY
SHIFT IN
However, OR will remain LOW, indicating data at the output is not valid.
until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.
for one internal cycle (at least t
they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset
is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.
devices.
flags. This need is due to the variation of delays of the FIFOs.
INPUT READY
[13, 14, 15, 16, 17]
DATA IN
SHIFT IN
MR
ORL
) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO,
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
0
1
2
3
0
1
2
3
0
1
2
3
MR
MR
MR
SI
IR
DI
DI
DI
DI
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
SO
OR
SO
OR
SO
OR
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
MR
192 x 12 Application
128 x 4 Application
DO
DO
DO
DO
OR
SO
0
1
2
3
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
0
1
2
3
0
1
2
3
0
1
2
3
MR
MR
MR
8
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
OR
OR
OR
SO
SO
SO
0
1
2
3
0
1
2
3
0
1
2
3
SI
IR
DI
DI
DI
DI
0
1
2
3
[19]
[18]
MR
DO
DO
DO
DO
OR
SO
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
IR
SI
DI
DI
DI
DI
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
C401–16
MR
MR
MR
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
SO
OR
SO
OR
SO
OR
0
1
2
3
0
1
2
3
0
1
2
3
CY7C401/CY7C403
CY7C402/CY7C404
OUTPUT READY
SHIFT OUT
DATA OUT
COMPOSITE
OUTPUT READY
SHIFT OUT
C401–17
MR