IDT74FCT162952CTPA IDT, Integrated Device Technology Inc, IDT74FCT162952CTPA Datasheet - Page 3

• Manufacturer Part Number: IDT74FCT162952CTPA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74FCT162952CTPA

• Operating Supply Voltage (typ): 5V
• Propagation Delay Time: 6.3ns
• Number Of Channels: 16
• Output Type: 3-State
• Package Type: TSSOP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
Symbol
V
T
T
X(0:15)
Y(0:15)
Z(0:15)
I
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
conditions for extended periods may affect reliability.
Signal
TERM
PATH
OUT
LEXY
LEYX
LEXZ
LEZX
T
BIAS
P
STG
OEU
OEL
T/
A
T
R
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
I/O
I/O
I/O
I/O
Rating
I
I
I
I
I
I
I
I
Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
Bidirectional Data port Y. Connected to the even path or even bank of memory.
Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXY
Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXZ.
Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even
path Y is latched on the HIGH-to-LOW transition of LEYX.
Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd
path Z is latched on the HIGH-to-LOW transition of LEZX
Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even
path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).
Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,
Port X is an output Port while Ports Y & Z are input Ports
Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/
Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/
Exposure to absolute maximum rating
–0.5 to +7.0
–55 to +125
–55 to +125
0 to +70
Com’l.
1.0
50
(1)
–0.5 to +7.0
–55 to +125
–65 to +135
–65 to +125
R
R
Mil.
1.0
50
.
.
2527 tbl 03
mA
Unit
W
V
C
C
C
11.5
CAPACITANCE
NOTE:
1. This parameter is guaranteed by device characterization, but is not prod-
TRUTH TABLE
NOTES:
1. For Z X and X Z transfers, Y-port output buffers are tristated.
2. For Y X and X Y transfers, Z-port output buffers are tristated.
Symbol
Path
C
Description
uction tested.
C
L
H
L
OUT
H
X
X
X
IN
T/
Input Capacitance
Output Capacitance
H
H
X
X
X
L
L
R R
Parameter
OEU
OEU
L
L
L
L
H
H
L
(T
A
= +25 C, F = 1.0MH
(1)
OEL
COMMERCIAL TEMPERATURE RANGE
OEL
H
L
L
L
L
L
H
Functionality
Z X (16-bits)–Read Z
X Z (16 bits)–Write Z
Y X (16-bits)–Read Y
X Y (16 bits)–Write Y
All output buffers are
disabled
Transfer of lower 8 bits
(0:7) as per PATH & T/
Transfer of upper 8 bits
(8:15) as per PATH & T/
Conditions
V
V
OUT
IN
= 0V
= 0V
Z
)
Max.
12
8
2527 tbl 04
2527 tbl 01
2527 tbl 02
(1)
(2)
(2)
R
(1)
Unit
pF
pF
R
3