MC14568BCP ON Semiconductor, MC14568BCP Datasheet

MC14568BCP

Manufacturer Part Number
MC14568BCP
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC14568BCP

Operating Temperature (max)
125C
Package Type
PDIP
Pin Count
16
Mounting
Through Hole
Lead Free Status / Rohs Status
Not Compliant

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase Comparator and
Programmable Counters
100 counter and a programmable divide–by–N 4–bit binary counter (all
positive–edge triggered) constructed with MOS P–channel and N–channel
enhancement mode devices (complementary MOS) in a monolithic structure.
programmable divide–by–N counter for frequency synthesizers and phase–
locked loop applications requiring low power dissipation and/or high noise
immunity.
the second counter connected to the phase comparator (CTL high), or used
independently of the programmable divide–by–N counter, for example
cascaded with a MC14569B, MC14522B or MC14526B (CTL low).
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
REV 3
1/94
MAXIMUM RATINGS*
PC in 14
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation, per Package†
Operating Temperature Range
Storage Temperature Range
CTL 15
MOTOROLA CMOS LOGIC DATA
PE 2
The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or
The MC14568B has been designed for use in conjunction with a
This device can be used with both counters cascaded and the output of
C1 9
Motorola, Inc. 1995
“0” 3
Supply Voltage Range = 3.0 to 18 V
Capable of Driving Two Low–Power TTL Loads, One Low–Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range.
Chip Complexity: 549 FETs or 137 Equivalent Gates
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
V DD = PIN 16
V SS = PIN 8
TG
(REF.)
Rating
TG
D P3
BLOCK DIAGRAM
(Voltages referenced to V SS )
A
B
4
PROGRAMMABLE
COMPARATOR
COUNTER D1
COUNTER D2
D P2 D P1
PHASE
5
4–BIT
6
7
Symbol
D P0
V DD
T stg
V in
P D
T A
I in
TG
– 0.5 to V DD + 0.5
– 55 to + 125
– 65 to + 150
– 0.5 to + 18
Value
13 PC out
12 LD
11 G
10 F
1 Q1/C2
500
10
PC in
C1
“0”
mAdc
Unit
Vdc
Vdc
mW
_ C
_ C
CTL HIGH
P/C
D1
D2
The divide by zero state on the pro-
grammable divide–by–N 4–bit binary
counter, D2, is illegal.
Q1/C2
T A = – 55 to 125 C for all packages.
Pin 10
PC out
LD
ORDERING INFORMATION
F
0
0
1
1
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
MC14568B
PC in
TRUTH TABLE
Pin 11
C1
“0”
G
0
1
0
1
CTL LOW
Division Ratio
of Counter D1
CASE 751B
P/C
CERAMIC
CASE 620
CASE 648
D SUFFIX
L SUFFIX
P SUFFIX
D1
D2
PLASTIC
Plastic
Ceramic
SOIC
100
16
64
SOIC
4
MC14568B
PC out
LD
Q1/C2
1

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MC14568BCP Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Phase Comparator and Programmable Counters The MC14568B consists of a phase comparator, a divide–by–4, 16 100 counter and a programmable divide–by–N 4–bit binary counter (all positive–edge triggered) constructed with MOS P–channel and N–channel enhancement ...

Page 2

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

SWITCHING TIME TEST CIRCUITS AND WAVEFORMS CTL out PULSE PC in GENERATOR 1 F Q1/C2 G PULSE C1 “0” GENERATOR ...

Page 5

(REF “0” COUNTER MOTOROLA CMOS LOGIC DATA LOGIC DIAGRAM ...

Page 6

Typical Maximum Frequency Divider D1 Division ratios 100 ( pF – 40 – ...

Page 7

The MC14568B contains a phase comparator, a fixed divider ( 4, 16, 64, 100) and a programmable divide– by–N 4–bit counter. PHASE COMPARATOR The phase comparator is a positive edge controlled logic circuit. It essentially consists of four flip–flops and ...

Page 8

If used in cascade with the programmable divide–by–N counter, practically all usual reference frequencies, or chan- nel spacings of 25, 20, 12.5, 10, 6.25 kHz, etc. are easily achievable. PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2) This counter is programmable by using ...

Page 9

out C1 (5 MHz) MC14568B ( CTL “0” DP0 – – – – – DP3 – 5) (625 kHz STEPS) Divide ratio = 160N 1 + 16N 2 ...

Page 10

Figure 9. Typical 23–Channel CB Frequency Synthesizer for MC14568B 10 Double Conversion Transceivers MOTOROLA CMOS LOGIC DATA ...

Page 11

N SEATING PLANE 0.25 (0.010 –A– 0.25 (0.010) M MOTOROLA CMOS LOGIC ...

Page 12

G K –T– SEATING PLANE 0.25 (0.010 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding ...

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