A54SX08A-FTQ100 MICROSEMI, A54SX08A-FTQ100 Datasheet - Page 34

• Manufacturer Part Number: A54SX08A-FTQ100
• Manufacturer: MICROSEMI

Specifications of A54SX08A-FTQ100

• Family Name: SX-A
• Number Of Usable Gates: 8000
• Number Of Logic Blocks/elements: 768
• # Registers: 512
• # I/os (max): 81
• Frequency (max): 172MHz
• Process Technology: 0.25um/0.22um (CMOS)
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 512
• Device System Gates: 12000
• Propagation Delay Time: 1.7ns
• Operating Supply Voltage (min): 2.25V
• Operating Supply Voltage (max): 2.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

SX-A Timing Model
Note: *Values shown for A54SX72A, –2, worst-case commercial conditions at 5 V PCI with standard place-and-route.
Figure 2-3 • SX-A Timing Model
Sample Path Calculations
Hardwired Clock
2 -1 4
External Setup
Clock-to-Out (Pad-to-Pad) = t
SX-A Family FPGAs
Routed
Clock
Hardwired
Clock
I/O Module
I/O Module
t
t
Input Delays
INYH
INYH
t
HCKH
t
(100% Load)
RCKH
= 0.6 ns
= 0.6 ns
= (t
= 0.6 + 0.3 + 0.8 - 1.8 = – 0.1 ns
= 1.8 + 0.8 + 0.3 + 3.9 = 6.8 ns
= 1.8 ns
= 3.0 ns
HCKH
INYH
+ t
+ t
t
t
RCO
RD1
t
t
RD1
RD2
t
t
SUD
HD
SUD
HD
= 0.0 ns
+ t
+ t
= 0.0 ns
= 0.3 ns
= 0.5 ns
= 0.8 ns
= 0.8 ns
SUD
RD1
) – t
+ t
DHL
HCKH
t
t
Register
RCO
RCO
D
D
Register
Cell
Internal Delays
Combinatorial
Cell
v5.3
t
= 0.8 ns
= 0.8 ns
PD
Cell
Q
Q
= 1.1 ns
Routed Clock
External Setup
Clock-to-Out (Pad-to-Pad) = t
t
t
RD1
RD1
= 0.3 ns
= 0.3 ns
t
t
t
RD1
RD4
RD8
Predicted
Routing
Delays
= 0.3 ns
= 0.9 ns
= 1.5 ns
t
t
t
t
DHL
ENZL
DHL
ENZL
I/O Module
I/O Module
= 3.9 ns
= 3.9 ns
= 1.5 ns
= 1.5 ns
I/O Module
= (t
= 0.6 + 0.3 + 0.8 - 3.0 = –1.3 ns
= 3.0 + 0.8 + 0.3 + 3.9 = 8.0 ns
Output Delays
RCKH
INYH
t
DHL
+ t
+ t
= 3.9 ns
RCO
RD1
+ t
+ t
RD1
SUD
) – t
+ t
DHL
RCKH