DG534ADJ Vishay, DG534ADJ Datasheet - Page 16

• Manufacturer Part Number: DG534ADJ
• Description: Analog Multiplexer Single 4:1 20-Pin PDIP
• Manufacturer: Vishay
• Type: Analog Multiplexerr

Specifications of DG534ADJ

• Multiplexer Configuration: Single 4:1
• Number Of Inputs: 4
• Number Of Outputs: 2
• Number Of Channels: 1
• Package Type: PDIP
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 10V
• Single Supply Voltage (typ): 12/15V
• Single Supply Voltage (max): 18V
• Dual Supply Voltage (min): ±10V
• Dual Supply Voltage (typ): ±12V
• Dual Supply Voltage (max): ±15V
• Power Dissipation: 625mW
• Mounting: Through Hole
• Pin Count: 20
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package: 20PDIP
• Maximum On Resistance: 90@15V@-3V Ohm
• Maximum Propagation Delay Bus To Bus: 300@15V|300@-3V ns
• Maximum High Level Output Current: 40 mA
• Multiplexer Architecture: 4:1
• Number Of Channels Per Chip: 1
• Maximum Turn-off Time: 175@15V@-3V ns
• Maximum Turn-on Time: 300@15V@-3V ns
• Power Supply Type: Single|Dual
• Lead Free Status / Rohs Status: Not Compliant

A typical switching threshold versus V
These devices feature an address readback (Tally) facility,
whereby the last address written to the device may be output
to the system. This allows improved status monitoring and
hand shaking without additional external components.
This function is controlled by the I/O pin, which directly
addresses the tri-state buffers connected to the EN and
address pins. EN and address pins can be assigned to accept
data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O =
1; WR = 1; RS = 1), or to reflect a high impedance and latched
state (when I/O = 0; WR = 1; RS = 1).
When I/O is high, the address output can sink or source
current. Note that V
point must be respected if V
shifting.
Further control pins facilitate easy microprocessor interface.
On chip address, data latches are activated by WR, which
serves as a strobe type function eliminating the need for
peripheral latch or memory I/O port devices. Also, for ease of
interface, a direct reset function (RS) allows all latches to be
cleared and switches opened. Reset should be used during
power up, etc., to avoid spurious switch action. See Figure 16.
www.vishay.com
16
DG534A/538A
Vishay Siliconix
Address Bus
Data Bus
L
is the logic high output condition. This
Reset
WR
L
is varied for input logic threshold
Address
Decoder
L
is shown in Figure 15.
FIGURE 16. DG534A in a Video Matrix
I/O
Video
Bus
Channel address data can only be entered during WR low,
when the address latches are transparent and I/O is low.
Similarly, address readback is only operational when WR and
I/O are high.
The Siliconix CLC410 Video amplifier is recommended as an
output buffer to reduce insertion loss and to drive coaxial
cables. For low power video routing applications or for unity
gain input buffers CLC111/CLC114 are recommended.
V
(V)
th
Data
Bus
S
S
EN
RS
WR
S
S
EN
RS
WR
A
A
A1
B2
A1
B2
0
0
DG534A
DG534A
8
7
6
5
4
3
2
1
0
FIGURE 15. Switching Threshold Voltage vs. V
, A
, A
0
1
1
2
D
D
D
D
A
B
A
B
4
CLC410
CLC410
CLC410
CLC410
6
A
V
= 2
8
V
75 W
75 W
75 W
75 W
L
(V)
10
12
S-05734—Rev. G, 29-Jan-02
Document Number: 70069
14
16
18
L